Arithmetic circuit and method of driving the same

ABSTRACT

In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No. 13/471,630, filed May 15, 2012, now allowed, which claims the benefit of a foreign priority application filed in Japan as Serial No. 2011-112834 on May 19, 2011, both of which are incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

An embodiment of the present invention relates to an arithmetic circuit.

2. Description of the Related Art

In recent years, for higher performance of an electronic appliance, an arithmetic processing unit in which one chip includes a circuit having a plurality of functions, such as a system LSI, has been developed.

In the above arithmetic processing unit, for example, functional circuits including a CMOS circuit, such as an arithmetic circuit and a storage circuit, are provided separately over one substrate, and data is transferred between the arithmetic circuit and the storage circuit through a wiring serving as a data bus (for example, see Patent Document 1).

Further, an arithmetic circuit which includes a storage means so as to have a function of performing a logic operation processing and storing data has been proposed. In the arithmetic circuit, data on the result of the logic operation processing can be stored without transferring the data through the data bus, so that the power consumption can be reduced.

REFERENCE Patent Document

-   [Patent Document 1] Japanese Published Patent Application No.     2010-282721

SUMMARY OF THE INVENTION

However, in a conventional arithmetic circuit, data of the arithmetic circuit to be stored needs to be separately saved in a nonvolatile storage circuit because a storage means of the conventional arithmetic circuit is volatile. Power is accordingly consumed in saving the data; therefore, the power consumption of the conventional arithmetic circuit is not sufficiently low.

Further, the conventional arithmetic circuit has a problem in that the storage means includes a large number of elements and that the circuit has a large area.

An object of an embodiment of the invention is to reduce power consumption. Another object of an embodiment of the invention is to reduce the power consumption and circuit area.

An embodiment of the invention provides an arithmetic circuit having a function of performing a logic operation processing and storing data on the result of the logic operation processing, which is configured as follows. The arithmetic circuit includes an arithmetic portion, a first transistor controlling whether a potential of an output signal is set at a potential corresponding to the result of the logic operation processing in the arithmetic portion, and a second transistor controlling whether the potential of the output signal is set at a potential corresponding to a reference potential. Further, a field-effect transistor with low off-state current is used as each of the first and second transistors.

In the above arithmetic circuit, by turning off the first and second transistors, the data can be held in the arithmetic circuit. Further, by maintaining the off states of the first and second transistors, the data can be stored for a long time.

An embodiment of the invention is an arithmetic circuit having a function of performing a logic operation processing based on an input signal, holding a potential corresponding to a result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a potential of the stored data is set at the potential corresponding to the result of the logic operation processing, and a second field-effect transistor controlling whether the potential of the stored data is set at a reference potential. Further, an off-state current per micrometer of channel width of each of the first and second field-effect transistors is lower than or equal to 10 aA.

According to an embodiment of the invention, data can be held with the power consumption suppressed; therefore, the power consumption can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A to 1C illustrate an example of an arithmetic circuit;

FIG. 2 illustrates an example of an arithmetic circuit;

FIGS. 3A to 3C illustrate examples of an arithmetic circuit;

FIGS. 4A to 4C illustrate examples of an arithmetic circuit;

FIGS. 5A and 5B illustrate an example of an arithmetic circuit;

FIG. 6 illustrates an example of an arithmetic circuit;

FIGS. 7A and 7B illustrate structural examples of a transistor;

FIGS. 8A to 8E illustrate a structural example of CAAC;

FIGS. 9A to 9C illustrate a structural example of CAAC;

FIGS. 10A to 10C illustrate a structural example of CAAC;

FIGS. 11A and 11B illustrate structural examples of CAAC;

FIGS. 12A to 12E illustrate an example of a method of manufacturing a transistor;

FIG. 13 is a graph for showing the relation between defect density in an oxide semiconductor layer and field-effect mobility of a transistor;

FIGS. 14A and 14B illustrate cross-sectional structural examples of a transistor;

FIGS. 15A to 15C show the result of calculation of electrical characteristics of transistors;

FIGS. 16A to 16C show the result of calculation of electrical characteristics of transistors;

FIGS. 17A to 17C show the result of calculation of electrical characteristics of transistors;

FIGS. 18A to 18C show the result of measurement of electrical characteristics of a transistor;

FIGS. 19A and 19B show the result of measurement of electrical characteristics of transistors;

FIGS. 20A and 20B show the result of measurement of electrical characteristics of transistors;

FIG. 21 shows XRD spectra of oxide semiconductor layers used in transistors;

FIG. 22 shows characteristics of a transistor;

FIG. 23 shows characteristics of transistors;

FIGS. 24A and 24B show characteristics of transistors;

FIG. 25 illustrates an example of an arithmetic processing unit; and

FIGS. 26A to 26D each illustrate an example of an electronic appliance.

DETAILED DESCRIPTION OF THE INVENTION

Examples of embodiments describing the present invention will be described below with reference to the drawings. Note that it will be readily appreciated by those skilled in the art that details of the embodiments can be modified in various ways without departing from the spirit and scope of the invention. The invention is therefore not limited to the following description of the embodiments.

Note that the contents in different embodiments can be combined with one another as appropriate. In addition, the contents in different embodiments can be replaced with each other.

Further, the ordinal numbers such as “first” and “second” are used to avoid confusion between components and do not limit the number of each component.

(Embodiment 1)

This embodiment will show an example of an arithmetic circuit including a storage means and having a function of performing a logic operation processing and storing data on the result of the logic operation processing.

Examples of the arithmetic circuit in this embodiment will be described with reference to FIGS. 1A to 1C.

An arithmetic circuit in FIG. 1A includes an arithmetic portion 111, a transistor 121, a transistor 122, and an inverter 131. The arithmetic circuit in FIG. 1A has a function of performing a logic operation processing based on an input signal InA and outputting a signal with a potential corresponding to the result of the logic operation processing as an output signal OutQ.

The arithmetic portion 111 has a function of performing the logic operation processing. The input signal InA is input to the arithmetic portion 111. Note that a plurality of input signals InA which are different from one another may be used.

The arithmetic portion 111 includes a signal input terminal, a first terminal, and a second terminal. Here, the input signal InA is input to the signal input terminal, a potential Vb is given to the second terminal, and the arithmetic portion 111 performs the logic operation processing based on the input signal InA input to the signal input terminal. Further, the arithmetic portion 111 switches a conducting state or a non-conducting state between the first terminal and the second terminal depending on the result of the logic operation processing.

The transistor 121 has a function of controlling whether a potential of the output signal OutQ is set at the potential corresponding to the result of the logic operation processing in the arithmetic portion 111.

An example of the transistor 121 is a field-effect transistor. Here, a potential of one of a source and a drain of the transistor 121 is set in accordance with the result of the logic operation processing in the arithmetic portion 111. Further, for example, a clock signal CLK1 is input to a gate of the transistor 121; however, without limitation, another signal or voltage may be applied to the gate of the transistor 121 so that the state of the transistor 121 can be changed.

The transistor 122 has a function of controlling whether the potential of the output signal OutQ is set at a reference potential.

An example of the transistor 122 is a field-effect transistor. Here, a potential Va serving as the reference potential is given to one of a source and a drain of the transistor 122. The other of the source and the drain of the transistor 122 is electrically connected to the other of the source and the drain of the transistor 121; the connection portion is referred to as node FN. Further, for example, a clock signal CLK2 is input to a gate of the transistor 122; however, without limitation, another signal or voltage may be applied to the gate of the transistor 122 so that the state of the transistor 122 can be changed. In the arithmetic circuit in FIG. 1A, the value of the potential of the output signal OutQ is set in accordance with a potential of the node FN.

Further, the transistors 121 and 122 can each be a transistor with low off-state current. In that case, the off-state current per micrometer of channel width of the transistor is 10 aA (1×10⁻¹⁷ A) or lower, preferably 1 aA (1×10⁻¹⁸ A) or lower, more preferably 10 zA (1×10⁻²⁰ A) or lower, further preferably 1 zA (1×10⁻²¹ A) or lower, still further preferably 100 yA (1×10⁻²² A) or lower.

As the above transistor with low off-state current, it is possible to use a transistor including a semiconductor layer in which a channel is formed and which has a wider band gap than silicon, for example, 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. An example of the transistor having a wide band gap is a field-effect transistor including an oxide semiconductor layer in which a channel is formed.

Note that in FIG. 1A, the transistors 121 and 122 are each denoted by a circuit symbol for a transistor including the oxide semiconductor layer as an example, but are not limited to that transistor.

Note that one of the potentials Va and Vb is a high power supply potential Vdd, and the other is a low power supply potential Vss. The high power supply potential Vdd has a value relatively higher than the low power supply potential Vss, whereas the low power supply potential Vss has a value relatively lower than the high power supply potential Vdd. The values of the potentials Va and Vb might interchange depending on the conductivity type of the transistor, for example. Further, a difference between the potentials Va and Vb may be used as a power supply voltage.

As the clock signal CLK1, for example, a clock signal whose phase is delayed from that of the clock signal CLK2 by less than 1 cycle can be used.

The inverter 131 has a function of outputting a signal with a potential corresponding to the potential of the node FN. In the arithmetic circuit in FIG. 1A, the signal output from the inverter 131 is the output signal OutQ. A signal with the potential of the node FN is input to the inverter 131, and the inverter 131 outputs the output signal OutQ with a potential corresponding to the input signal. Note that the inverter 131 is not necessarily provided as long as charge can be held at the node FN. For example, a switch or a buffer may be provided instead of the inverter 131.

Next, as an example of a method of driving the arithmetic circuit in this embodiment, an example of a method of driving the arithmetic circuit in FIG. 1A will be described with reference to timing charts shown in FIGS. 1B and 1C. Here, for example, the transistors 121 and 122 are n-channel field-effect transistors including the above oxide semiconductor layer. Further, high-level potentials of the clock signals CLK1 and CLK2 are referred to as potential VH, and low-level potentials of the clock signals CLK1 and CLK2 are referred to as potential VL. Furthermore, the potential Va is a power supply potential Vdd, and the potential Vb is a ground potential Vgnd.

First, an off state of the transistor 121 is maintained, and the transistor 122 is turned on. For example, in periods T11 in FIGS. 1B and 1C, by setting the clock signal CLK1 at a low level, the off state of the transistor 121 is maintained, and by setting the clock signal CLK2 at a high level, the transistor 122 is turned on.

At this time, the value of the potential of the node FN becomes equivalent to that of the potential Va. Thus, the node FN is precharged. Further, the output signal OutQ is at a low level.

Next, the transistor 121 is turned on and the transistor 122 is turned off. For example, in periods T12 after the periods T11 in FIGS. 1B and 1C, by setting the clock signal CLK1 at a high level, the transistor 121 is turned on, and by setting the clock signal CLK2 at a low level, the transistor 122 is turned off.

At this time, the potential of the node FN is set in accordance with the result of the logic operation processing in the arithmetic portion 111. For example, in the case where the first terminal and the second terminal of the arithmetic portion 111 are brought into conduction in accordance with the result of the logic operation processing in the arithmetic portion 111 and a potential of the one of the source and the drain of the transistor 121 is set at the potential Vb, as shown in the period T12 in FIG. 1B, charge at the node FN is gradually released, and when the potential of the node FN becomes lower than or equal to a potential Vx, the output signal OutQ changes from the low level to a high level. After that, the potential of the node FN becomes equivalent to the potential Vb. Further, in the case where the first terminal and the second terminal in the arithmetic portion 111 are in a non-conducting state, as shown in the period T12 in FIG. 1C, the output signal OutQ remains at the low level. In this manner, the arithmetic processing can be performed based on the input signal InA through the periods T11 and T12.

The arithmetic circuit illustrated in FIG. 1A also has a function of storing data. For example, in periods T13 after the periods T12 in FIGS. 1B and 1C, by turning off the transistor 121 and maintaining the off state of the transistor 122, the arithmetic circuit holds the potential at the node FN as stored data. At this time, the potential of the output signal OutQ is also held.

Further, in the case where the transistors 121 and 122 are each a normally-off type transistor, the supply of the power supply voltage to the arithmetic circuit can be stopped. In order to stop the supply of the power supply voltage to the arithmetic circuit, first, the clock signals CLK1 and CLK2 are set at low levels and then the supply of the clock signals CLK1 and CLK2 to the arithmetic circuit is stopped. After that, the supply of the power supply voltage to the arithmetic circuit is stopped.

At this time, the values of potentials of the gates of the transistors 121 and 122 become equivalent to the low levels, so that the transistors 121 and 122 are brought into off states. However, the value of the stored data (the potential of the node FN) in the arithmetic circuit remains held.

The above description is the example of the method of driving the arithmetic circuit in FIG. 1A.

The arithmetic circuit in FIG. 1A can perform a variety of logic operations depending on the configuration of the arithmetic portion 111. Examples of the configuration of the arithmetic circuit in FIG. 1A are illustrated in FIG. 2, FIGS. 3A to 3C, and FIGS. 4A to 4C.

An arithmetic circuit in FIG. 2 is an example of an arithmetic circuit performing a NOT operation. In the arithmetic circuit in FIG. 2, the arithmetic portion 111 includes a transistor 151 which is a p-channel field-effect transistor so as to perform the NOT operation. In this case, one of a source and a drain of the transistor 151 is electrically connected to the one of the source and the drain of the transistor 121, the potential Vb is given to the other of the source and the drain of the transistor 151, and the input signal InA is input to a gate of the transistor 151.

An arithmetic circuit in FIG. 3A is an example of an arithmetic circuit performing an AND operation. In the arithmetic circuit in FIG. 3A, the arithmetic portion 111 includes a transistor 161 and a transistor 162 which are n-channel field-effect transistors so as to perform the AND operation. In this case, one of a source and a drain of the transistor 161 is electrically connected to the one of the source and the drain of the transistor 121, and an input signal InA_1 is input to a gate of the transistor 161. Further, one of a source and a drain of the transistor 162 is electrically connected to the other of the source and the drain of the transistor 161, the potential Vb is given to the other of the source and the drain of the transistor 162, and an input signal InA_2 is input to a gate of the transistor 162.

An arithmetic circuit in FIG. 3B is an example of an arithmetic circuit performing an OR operation. In the arithmetic circuit in FIG. 3B, the arithmetic portion 111 includes a transistor 171 and a transistor 172 which are p-channel field-effect transistors so as to perform the OR operation. In this case, one of a source and a drain of the transistor 171 is electrically connected to the one of the source and the drain of the transistor 121, the potential Vb is given to the other of the source and the drain of the transistor 171, and the input signal InA_1 is input to a gate of the transistor 171. Further, one of a source and a drain of the transistor 172 is electrically connected to the one of the source and the drain of the transistor 121, the potential Vb is given to the other of the source and the drain of the transistor 172, and an input signal InA_2 is input to a gate of the transistor 172.

An arithmetic circuit in FIG. 3C is an example of an arithmetic circuit performing an ENOR operation. In the arithmetic circuit in FIG. 3C, the arithmetic portion 111 includes a transistor 181 and a transistor 182 which are n-channel field-effect transistors, and a transistor 183 and a transistor 184 which are p-channel field-effect transistors so as to perform the ENOR operation. In this case, one of a source and a drain of the transistor 181 is electrically connected to the one of the source and the drain of the transistor 121, and the input signal InA_1 is input to a gate of the transistor 181. Further, one of a source and a drain of the transistor 182 is electrically connected to the other of the source and the drain of the transistor 181, the potential Vb is given to the other of the source and the drain of the transistor 182, and the input signal InA_2 is input to a gate of the transistor 182. Furthermore, one of a source and a drain of the transistor 183 is electrically connected to the one of the source and the drain of the transistor 121, and the input signal InA_1 is input to a gate of the transistor 183. Furthermore, one of a source and a drain of the transistor 184 is electrically connected to the other of the source and the drain of the transistor 183, the potential Vb is given to the other of the source and the drain of the transistor 184, and the input signal InA_2 is input to a gate of the transistor 184.

Note that as illustrated in FIG. 4A, by replacing the transistors 161 and 162 in FIG. 3A with p-channel field-effect transistors, the arithmetic circuit can perform a NAND operation. Further, as illustrated in FIG. 4B, by replacing the transistors 171 and 172 in FIG. 3B with n-channel field-effect transistors, the arithmetic circuit can perform a NOR operation. Furthermore, as illustrated in FIG. 4C, by replacing the transistor 182 in FIG. 3C with a p-channel field-effect transistor and the transistor 184 in FIG. 3C with an n-channel field-effect transistor, the arithmetic circuit can perform an EOR operation.

Examples of the arithmetic circuit in this embodiment are not limited to the above configurations; for example, a plurality of arithmetic circuits illustrated in any of FIGS. 1A to 1C, FIG. 2, FIGS. 3A to 3C, and FIGS. 4A to 4C may be included in an arithmetic circuit which outputs a plurality of signals as output signals.

As described with reference to FIGS. 1A to 1C, FIG. 2, FIGS. 3A to 3C, and FIGS. 4A to 4C, the arithmetic circuit exemplified in this embodiment includes the arithmetic portion performing the logic operation processing, the first transistor (e.g., the transistor 121) controlling whether the potential of the output signal is set at the potential corresponding to the result of the logic operation processing in the arithmetic portion, and the second transistor (e.g., the transistor 122) controlling whether the potential of the output signal is set at the potential corresponding to the reference potential, thereby having a function of performing the logic operation processing and storing data. For example, by turning off the first and second transistors, the data can be stored in the arithmetic circuit without using a storage capacitor or the like. The above structure does not need a complementary structure of the arithmetic circuit; therefore, the arithmetic circuit can have a smaller number of transistors than in the case where a CMOS circuit is used. Further, the arithmetic circuit without a complementary structure can have a smaller number of signal lines than in the case where a CMOS circuit is used, which can result in a reduction in circuit area. Furthermore, the arithmetic circuit without a complementary structure can have lower through current than in the case where a CMOS circuit is used, which can result in a reduction in power consumption.

In the example of the arithmetic circuit according to this embodiment, the field-effect transistor with low off-state current is used as each of the first and second transistors; therefore, the transistor in an off state can have reduced leakage current. Accordingly, the data can be held for a long time and does not need to be separately saved in a nonvolatile storage circuit; therefore, the operation speed can be increased and the power consumption can be reduced.

Table 1 shows comparison between a magnetic tunnel junction element (also referred to as MTJ element) used in an MRAM and the above nonvolatile storage circuit including a stack (also referred to as OS/Si) of a transistor including an oxide semiconductor and a transistor including a silicon semiconductor.

TABLE 1 Spintronics (MTJ element) OS/Si 1. Heat resistance Curie temperature Process temperature 500° C. (Reliability 150° C.) 2. Driving method Current driving Voltage driving 3. Writing principle Changing spin direction of On/off of FET magnetic body 4. Si LSI Suitable for bipolar LSI Suitable for MOS LSI (MOS device is preferable for high integration because bipolar device is unsuitable for high integration. Note that W gets larger.) 5. Overhead Large Smaller by 2 to 3 or more orders of (due to high Joule heat) magnitude than the MTJ element (due to charging and discharging of parasitic capacitance) 6. Nonvolatility Utilizing spin Utilizing low off-state current 7. Number of reading Without limitation Without limitation times 8. 3D conversion Difficult Easy (at most two layers) (the number of layers is limitless) 9. Integration degree 4 F² to 15 F² Depends on the number of layers (F²) stacked in 3D conversion (it is necessary to ensure heat resistance in process of forming upper OS FET) 10. Material Magnetic rare-earth element Oxide semiconductor material 11. Bit cost High Low (possibly slightly high depending on oxide semiconductor material (such as In)) 12. Resistance to Low High magnetic field

The MTJ element is disadvantageous in that magnetism is lost when the temperature is the Curie temperature or higher because a magnetic material is used. In addition, the MTJ element is compatible with a silicon bipolar device because current driving is employed; however, the bipolar device is unsuitable for high integration. Furthermore, the MTJ element has a problem in that its power consumption is increased with an increase in write current due to an increase in memory capacitance.

The MTJ element has low resistance to a magnetic field, so that the spin direction is likely to change when the MTJ element is exposed to a high magnetic field. Further, magnetic fluctuation is caused by nanoscaling of a magnetic body used for the MTJ element.

The material cost per bit of the MTJ element is expensive.

On the other hand, the transistor formed using an oxide semiconductor in this embodiment has an element structure and an operation principle which are similar to those of a silicon MOSFET except that a semiconductor material of a channel is a metal oxide. Further, the transistor formed using an oxide semiconductor is not influenced by a magnetic field, and does not cause soft errors. This shows that the transistor is highly conformable to a silicon integrated circuit.

(Embodiment 2)

This embodiment will show an example of an arithmetic circuit which is a full adder, as another example of the arithmetic circuit in Embodiment 1.

First, a configuration example of the arithmetic circuit in this embodiment will be described with reference to FIGS. 5A and 5B.

A signal A, a signal B, and a signal C (carry signal from a lower digit) are input as input signals InA to an arithmetic circuit in FIG. 5A, and the arithmetic circuit in FIG. 5A has a function of performing an addition processing based on the signals A, B, and C, and outputting a signal C⁺ (carry signal to the subsequent digit) and a signal S (signal of the addition result) as output signals OutQ.

The arithmetic circuit in FIG. 5A includes an arithmetic portion 311, a transistor 321_1, a transistor 322_1, an inverter 331_1, a transistor 321_2, a transistor 322_2, and an inverter 331_2.

The arithmetic portion 311 has a function of performing a logic operation processing. The signals A, B, and C are input to the arithmetic portion 311.

The transistor 321_1 has a function of controlling whether a potential of the signal C⁺ is set at a potential corresponding to the result of the logic operation processing in the arithmetic portion 311.

The transistor 321_1 is an n-channel field-effect transistor. The clock signal CLK1 is input to a gate of the transistor 321_1. One of a source and a drain of the transistor 321_1 is electrically connected to the arithmetic portion 311.

The transistor 322_1 has a function of controlling whether the potential of the signal C⁺ is set at a potential corresponding to a reference potential.

The transistor 322_1 is an n-channel field-effect transistor. The clock signal CLK2 is input to a gate of the transistor 322_1, and the power supply potential Vdd is given to one of a source and a drain of the transistor 322_1. The other of the source and the drain of the transistor 322_1 is electrically connected to the other of the source and the drain of the transistor 321_1; the connection portion is referred to as node FN_31.

The inverter 331_1 has a function of outputting a signal with a potential corresponding to a potential of the node FN_31. At this time, the inverter 331_1 outputs the signal C⁺ as the output signal.

The transistor 321_2 has a function of controlling whether a potential of the signal S is set at a potential corresponding to the result of the logic operation processing in the arithmetic portion 311.

The transistor 321_2 is an n-channel field-effect transistor. The clock signal CLK1 is input to a gate of the transistor 321_2. One of a source and a drain of the transistor 321_2 is electrically connected to the arithmetic portion 311.

The transistor 322_2 has a function of controlling whether the potential of the signal S is set at a potential corresponding to a reference potential.

The transistor 322_2 is an n-channel field-effect transistor. The clock signal CLK2 is input to a gate of the transistor 322_2, and the power supply potential Vdd is given to one of a source and a drain of the transistor 322_2. The other of the source and the drain of the transistor 322_2 is electrically connected to the other of the source and the drain of the transistor 321_2; the connection portion is referred to as node FN_32.

The inverter 331_2 has a function of outputting a signal with a potential corresponding to a potential of the node FN_32. At this time, the inverter 331_2 outputs the signal S as the output signal.

Examples of the transistors 321_1, 322_1, 321_2, and 322_2 are each be any field-effect transistor which can be used as the transistors 121 and 122 in FIG. 1A. Note that in FIG. 5A, the transistors 321_1, 322_1, 321_2, and 322_2 are each denoted by a circuit symbol for a transistor including the oxide semiconductor layer, but are not limited to the transistor.

As the clock signal CLK1, for example, a clock signal whose phase is delayed from that of the clock signal CLK2 by less than 1 cycle can be used.

The following will show a configuration example of the arithmetic portion 311.

The arithmetic portion 311 in FIG. 5A includes a transistor 351, a transistor 352, a transistor 353, a transistor 354, a transistor 355, a transistor 356, a transistor 357, a transistor 358, a transistor 359, a transistor 360, a transistor 361, a transistor 362, a transistor 363, a transistor 364, a transistor 365, and a transistor 366.

The transistor 351 is an n-channel field-effect transistor. One of a source and a drain of the transistor 351 is electrically connected to the one of the source and the drain of the transistor 321_1, and a signal A is input to a gate of the transistor 351.

The transistor 352 is an n-channel field-effect transistor. One of a source and a drain of the transistor 352 is electrically connected to the one of the source and the drain of the transistor 321_1, and a signal B is input to a gate of the transistor 352.

The transistor 353 is an n-channel field-effect transistor. One of a source and a drain of the transistor 353 is electrically connected to the other of the source and the drain of the transistor 351 and the other of the source and the drain of the transistor 352. The ground potential Vgnd is given to the other of the source and the drain of the transistor 353, and a signal C is input to a gate of the transistor 353.

The transistor 354 is an n-channel field-effect transistor. One of a source and a drain of the transistor 354 is electrically connected to the one of the source and the drain of the transistor 321_1, and the signal A is input to a gate of the transistor 354.

The transistor 355 is an n-channel field-effect transistor. One of a source and a drain of the transistor 355 is electrically connected to the other of the source and the drain of the transistor 354, and the signal B is input to a gate of the transistor 355.

The transistor 356 is an n-channel field-effect transistor. One of a source and a drain of the transistor 356 is electrically connected to the other of the source and the drain of the transistor 355. The ground potential Vgnd is given to the other of the source and the drain of the transistor 356, and a signal CB which is an inverted signal of the signal C is input to a gate of the transistor 356. For example, the signal CB can be generated by inverting the signal C by using an inverter or the like.

The transistor 357 is an n-channel field-effect transistor. One of a source and a drain of the transistor 357 is electrically connected to the one of the source and the drain of the transistor 321_2, and the signal A is input to a gate of the transistor 357.

The transistor 358 is an n-channel field-effect transistor. One of a source and a drain of the transistor 358 is electrically connected to the one of the source and the drain of the transistor 321_2, and the signal B is input to a gate of the transistor 358.

The transistor 359 is an n-channel field-effect transistor. One of a source and a drain of the transistor 359 is electrically connected to the other of the source and the drain of the transistor 357 and the other of the source and the drain of the transistor 358. A signal AB which is an inverted signal of the signal A is input to a gate of the transistor 359. For example, the signal AB can be generated by inverting the signal A by using an inverter or the like.

The transistor 360 is an n-channel field-effect transistor. One of a source and a drain of the transistor 360 is electrically connected to the other of the source and the drain of the transistor 357 and the other of the source and the drain of the transistor 358. A signal BB which is an inverted signal of the signal B is input to a gate of the transistor 360. For example, the signal BB can be generated by inverting the signal B by using an inverter or the like.

The transistor 361 is an n-channel field-effect transistor. One of a source and a drain of the transistor 361 is electrically connected to the other of the source and the drain of the transistor 359 and the other of the source and the drain of the transistor 360. The ground potential Vgnd is given to the other of the source and the drain of the transistor 361, and the signal C is input to a gate of the transistor 361.

The transistor 362 is an n-channel field-effect transistor. One of a source and a drain of the transistor 362 is electrically connected to the one of the source and the drain of the transistor 321_2, and the signal A is input to a gate of the transistor 362.

The transistor 363 is an n-channel field-effect transistor. One of a source and a drain of the transistor 363 is electrically connected to the one of the source and the drain of the transistor 321_2, and the signal AB is input to a gate of the transistor 363.

The transistor 364 is an n-channel field-effect transistor. One of a source and a drain of the transistor 364 is electrically connected to the other of the source and the drain of the transistor 362, and the signal B is input to a gate of the transistor 364.

The transistor 365 is an n-channel field-effect transistor. One of a source and a drain of the transistor 365 is electrically connected to the other of the source and the drain of the transistor 363, and the signal BB is input to a gate of the transistor 365.

The transistor 366 is an n-channel field-effect transistor. One of a source and a drain of the transistor 366 is electrically connected to the other of the source and the drain of the transistor 364 and the other of the source and the drain of the transistor 365. The ground potential Vgnd is given to the other of the source and the drain of the transistor 366, and the signal CB is input to a gate of the transistor 366.

As the transistors 351 to 366, it is possible to use transistors in each of which a semiconductor layer where a channel is formed includes a semiconductor belonging to Group 14 of the periodic table (e.g., silicon). In that case, the semiconductor layer may be a single crystal semiconductor layer, a polycrystalline semiconductor layer, a microcrystalline semiconductor layer, or an amorphous semiconductor layer.

The transistors 351 to 366 are all n-channel transistors; thus, the number of manufacturing steps can be reduced.

Note that the transistor gates to which the same signal is input may be electrically connected to one another. Further, the transistor terminals to which the same potential is supplied may be electrically connected to one another.

Next, as an example of a method of driving the arithmetic circuit in this embodiment, an example of a method of driving the arithmetic circuit in FIG. 5A will be described. Here, for example, data signals (the signals A, B, C, C⁺, and S) are digital signals, potentials of the data signals at high levels are referred to as data(1), and potentials of the data signals at low levels are referred to as data (0). Further, when the potential of the data signal is equivalent to the power supply potential Vdd, the data signal is at a high level, whereas when the data signal is equivalent to the ground potential Vgnd, the data signal is at a low level.

First, off states of the transistors 321_1 and 321_2 are maintained, and the transistors 322_1 and 322_2 are turned on. For example, by setting the clock signal CLK1 at a low level, the off states of the transistors 321_1 and 321_2 are maintained, and by setting the clock signal CLK2 at a high level, the transistors 322_1 and 322_2 are turned on.

At this time, values of potentials of the nodes FN_31 and FN_32 each become equivalent to that of the potential Va. Thus, the nodes FN_31 and FN_32 are precharged. Further, the signals C⁺ and S are at low levels.

Next, the transistors 322_1 and 322_2 are turned off, and the transistors 321_1 and 321_2 are turned on. For example, by setting the clock signal CLK1 at a high level, the transistors 321_1 and 321_2 are turned on, and by setting the clock signal CLK2 at a low level, the transistors 322_1 and 322_2 are turned off.

At this time, the potentials of the nodes FN_31 and FN_32 are set in accordance with the result of the logic operation processing in the arithmetic portion 311. The values of the signals C⁺ and S are determined depending on the values of the signals A, B, and C. FIG. 5B shows a truth table of the relations among the values of the signals A, B, C, C⁺, and S.

For example, as shown in FIG. 5B, in the case where the number of signals at high levels (data(1)) among the signals A, B, and C is two or more, the signal C⁺ is set at a high level (data(1)), and in the case where the number of signals at high levels (data(1)) among the signals A, B, and C is one or less, the signal C⁺ is set at a low level (data(0)). Further, in the case where the number of the signals at high levels (data(1)) among the signals A, B, and C is an odd number, the signal S is set at a low level (data(0)), and in the other cases, the signal S is set at a high level (data(1)).

The arithmetic circuit illustrated in FIG. 5A also has a function of storing data. For example, by turning off the transistors 321_1 and 321_2, the arithmetic circuit holds the potential of the node FN_31 as stored data M1 and the potential of the node FN_32 as stored data M2. At this time, the potentials of the signals C⁺ and S are also held.

Further, in the case where the transistors 321_1, 321_2, 322_1, and 322_2 are each a normally-off transistor, the supply of the power supply voltage to the arithmetic circuit can be stopped. In order to stop the supply of the power supply voltage to the arithmetic circuit, first, the clock signals CLK1 and CLK2 are set at low levels and then the supply of the clock signals CLK1 and CLK2 to the arithmetic circuit is stopped. After that, the supply of the power supply voltage to the arithmetic circuit is stopped.

At this time, the values of potentials of the gates of the transistors 321_1, 321_2, 322_1, and 322_2 become equivalent to the low levels, so that the transistors 321_1, 321_2, 322_1, and 322_2 are brought into off states. However, the values of the stored data M1 (the potential of the node FN_31) and the stored data M2 (the potential of the node FN_32) in the arithmetic circuit remain held.

The above description is the example of the method of driving the arithmetic circuit in FIG. 5A.

Note that the example of the arithmetic circuit in this embodiment is not limited to the above configuration; for example, as illustrated in FIG. 6, it is possible to replace the transistors 356, 359, 360, 363, 365, and 366 in the arithmetic portion 311 in FIG. 5A with p-channel field-effect transistors.

In that case, the signal C is input to the gate of the transistor 356 instead of the signal CB. The signal A is input to the gate of the transistor 359 instead of the signal AB. The signal B is input to the gate of the transistor 360 instead of the signal BB. The signal A is input to the gate of the transistor 363 instead of the signal AB. The signal B is input to the gate of the transistor 365 instead of the signal BB. The signal C is input to the gate of the transistor 366 instead of the signal CB.

Note that the description of the arithmetic circuit in FIG. 5A can be referred to for the same components as those in the arithmetic circuit in FIG. 5A. Further, the description of the example of the method of driving the arithmetic circuit in FIG. 5A can be referred to for the method of driving the arithmetic circuit in FIG. 6.

As illustrated in FIG. 6, the arithmetic portion 311 is composed of n-channel and p-channel field-effect transistors, so that the inverted signals of the signals A, B, and C are unnecessary, and the number of the input signals can be reduced. Further, the number of circuits such as inverters can also be reduced; therefore, the arithmetic circuit can have an even smaller circuit area.

As described with reference to FIGS. 5A and 5B and FIG. 6, the arithmetic circuit exemplified in this embodiment includes the arithmetic portion performing the logic operation processing, the first transistor (e.g., the transistor 321_1) controlling whether the potential of the signal C⁺ is set at the potential corresponding to the result of the logic operation processing in the arithmetic portion, the second transistor (e.g., the transistor 322_1) controlling whether the potential of the signal C⁺ is set at the potential i corresponding to the reference potential, a third transistor (e.g., the transistor 321_2) controlling whether the potential of the signal S is set at the potential corresponding to the result of the logic operation processing in the arithmetic portion, and a fourth transistor (e.g., the transistor 322_2) controlling whether the potential of the signal S is set at the reference potential, thereby having a function of performing the addition processing and storing data. The above structure does not need a complementary structure of the arithmetic circuit; therefore, the arithmetic circuit can have a smaller number of transistors than in the case where a CMOS circuit is used. Further, the arithmetic circuit without a complementary structure can have a smaller number of signal lines than in the case where a CMOS circuit is used, which can result in a reduction in circuit area. Furthermore, the arithmetic circuit without a complementary structure can have lower through current than in the case where a CMOS circuit is used, which can result in a reduction in power consumption.

In the example of the arithmetic circuit according to this embodiment, the field-effect transistor with low off-state current is used as each of the first to fourth transistors; therefore, the transistor in an off state can have reduced leakage current. Accordingly, the data does not need to be separately saved in a nonvolatile storage circuit; therefore, the operation speed can be increased and the power consumption can be reduced.

(Embodiment 3)

This embodiment will show examples of a field-effect transistor that includes an oxide semiconductor layer and can be applied to the transistor in the arithmetic circuit in the above embodiments.

Examples of structured of transistors in this embodiment will be described with reference to FIGS. 7A and 7B.

The transistor illustrated in FIG. 7A includes a conductive layer 601_a, an insulating layer 602_a, a semiconductor layer 603_a, a conductive layer 605 a_a, and a conductive layer 605 b_a.

The semiconductor layer 603_a includes a region 604 a_a and a region 604 b_a. The region 604 a_a and the region 604 b_a are positioned apart from each other and doped with a dopant. Note that a region between the region 604 a_a and the region 604 b_a serves as a channel formation region. The semiconductor layer 603_a is provided over an element formation layer 600_a. Note that it is not necessary to provide the region 604 a_a and the region 604 b_a.

The conductive layer 605 a_a and the conductive layer 605 b_a are provided over the semiconductor layer 603_a and electrically connected to the semiconductor layer 603_a. Side surfaces of the conductive layers 605 a_a and 605 b_a are tapered.

The conductive layer 605 a_a overlaps with part of the region 604 a_a; however, this embodiment is not limited to this structure. When the conductive layer 605 a_a overlaps with part of the region 604 a_a, the resistance between the conductive layer 605 a_a and the region 604 a_a can be low. Further, a region of the semiconductor layer 603_a which overlaps with the conductive layer 605 a_a may be all the region 604 a_a.

The conductive layer 605 b_a overlaps with part of the region 604 b_a; however, this embodiment is not limited to this structure. When the conductive layer 605 b_a overlaps with part of the region 604 b_a, the resistance between the conductive layer 605 b_a and the region 604 b_a can be low. Further, a region of the semiconductor layer 603_a which overlaps with the conductive layer 605 b_a may be all the region 604 b_a.

The insulating layer 602_a is provided over the semiconductor layer 603_a, the conductive layer 605 a_a, and the conductive layer 605 b_a.

The conductive layer 601_a is provided over part of the insulating layer 602_a, and overlaps with the semiconductor layer 603_a with the insulating layer 602_a placed therebetween. A region of the semiconductor layer 603_a, which overlaps with the conductive layer 601_a with the insulating layer 602_a placed therebetween, serves as the channel formation region.

The transistor illustrated in FIG. 7B includes a conductive layer 601_b, an insulating layer 602_b, a semiconductor layer 603_b, a conductive layer 605 a_b, a conductive layer 605 b_b, an insulating layer 606 a, an insulating layer 606 b, and an insulating layer 607.

The semiconductor layer 603_b includes a region 604 a_b and a region 604 b_b. The region 604 a_b and the region 604 b_b are positioned apart from each other and doped with a dopant. The semiconductor layer 603_b is provided over the conductive layers 605 a_b and 605 b_b and an element formation layer 600_b, for example, and electrically connected to the conductive layers 605 a_b and 605 b_b. Note that it is not necessary to provide the region 604 a_b and the region 604 b_b.

The insulating layer 602_b is provided over part of the semiconductor layer 603_b.

The conductive layer 601_b is provided over part of the insulating layer 602_b, and overlaps with the semiconductor layer 603_b with the insulating layer 602_b placed therebetween. A region of the semiconductor layer 603_b, which overlaps with the conductive layer 601_b with the insulating layer 602_b placed therebetween, serves as the channel formation region of the transistor. Note that an insulating layer may be provided over the conductive layer 601_b.

The insulating layer 606 a is provided over the insulating layer 602_b and is in contact with one of a pair of side surfaces of the conductive layer 601_b.

The insulating layer 606 b is provided over the insulating layer 602_b and is in contact with the other of the pair of side surfaces of the conductive layer 601_b.

Note that the dopant concentration in the portions of the regions 604 a_b and 604 b_b, which overlap with the insulating layers 606 a and 606 b with the insulating layer 602_b placed therebetween, may be lower than that of the portions of the regions 604 a_b and 604 b_b, which do not overlap with the insulating layers 606 a and 606 b.

The conductive layers 605 a_b and 605 b_b are provided over the semiconductor layer 603_b.

The conductive layer 605 a_b is electrically connected to the region 604 a_b and is in contact with the insulating layer 606 a.

The conductive layer 605 b_b is electrically connected to the region 604 b_b and is in contact with the insulating layer 606 b.

The insulating layer 607 is provided over the conductive layer 601_b, the conductive layers 605 a_b and 605 b_b, and the insulating layers 606 a and 606 b.

Next, the components illustrated in FIGS. 7A and 7B will be described.

As the element formation layers 600_a and 600_b, insulating layers or substrates having insulating surfaces can be used, for example. Further, layers over which elements are formed in advance can be used as the element formation layers 600_a and 600_b.

Each of the conductive layers 601_a and 601_b has a function of a gate of the transistor. Note that a layer functioning as a gate of the transistor can be called gate electrode or gate wiring.

As the conductive layers 601_a and 601_b, it is possible to use, for example, a layer of a metal material such as molybdenum, magnesium, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium or an alloy material containing any of these materials as a main component. Moreover, the conductive layers 601_a and 601_b can be a stack of layers containing materials applicable to the conductive layers 601_a and 601_b.

Each of the insulating layers 602_a and 602_b has a function of a gate insulating layer of the transistor.

Each of the insulating layers 602_a and 602_b can be, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, a hafnium oxide layer, or a lanthanum oxide layer. Moreover, the insulating layers 602_a and 602_b can be a stack of layers containing materials applicable to the insulating layers 602_a and 602_b.

Alternatively, as the insulating layers 602_a and 602_b, an insulating layer of a material containing, for example, an element that belongs to Group 13 in the periodic table and oxygen can be used. For example, when the semiconductor layers 603_a and 603_b contain a Group 13 element, the use of insulating layers containing a Group 13 element as insulating layers in contact with the semiconductor layers 603_a and 603_b makes the state of interfaces between the insulating layers and the oxide semiconductor layers favorable.

Examples of the material containing a Group 13 element and oxygen include gallium oxide, aluminum oxide, aluminum gallium oxide, and gallium aluminum oxide. Note that aluminum gallium oxide refers to a substance in which the amount of aluminum is larger than that of gallium in atomic percent, and gallium aluminum oxide refers to a substance in which the amount of gallium is larger than or equal to that of aluminum in atomic percent. For example, it is possible to use a material represented by Al₂O_(x) (x=3+α, where α is larger than 0 and smaller than 1), Ga₂O_(x) (x=3+α, where α is larger than 0 and smaller than 1), or Ga_(x)Al_(2−x)O_(3+α) (x is larger than 0 and smaller than 2 and α is larger than 0 and smaller than 1).

The insulating layers 602_a and 602_b can be a stack of layers of materials applicable to the insulating layers 602_a and 602_b. For example, the insulating layers 602_a and 602_b can be a stack of layers containing gallium oxide represented by Ga₂O_(x). Alternatively, the insulating layers 602_a and 602_b may be a stack of an insulating layer containing gallium oxide represented by Ga₂O_(x) and an insulating layer containing aluminum oxide represented by Al₂O_(x).

Each of the semiconductor layers 603_a and 603_b functions as a layer in which a channel of the transistor is formed. Examples of an oxide semiconductor applicable to the semiconductor layers 603_a and 603_b are In-based oxide (e.g., indium oxide), Sn-based oxide (e.g., tin oxide), and Zn-based oxide (e.g., zinc oxide).

As the metal oxide, a four-component metal oxide, a three-component metal oxide, or a two-component metal oxide can also be used, for example. Note that a metal oxide which can be used as the above oxide semiconductor may include gallium as a stabilizer for reducing variation in characteristics. A metal oxide which can be used as the above oxide semiconductor may include tin as the stabilizer. A metal oxide which can be used as the above oxide semiconductor may include hafnium as the stabilizer. A metal oxide which can be used as the above oxide semiconductor may include aluminum as the stabilizer. A metal oxide which can be used as the above oxide semiconductor may include one or more of the following materials as the stabilizer: lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium, which are lanthanoid. Further, the metal oxide that can be used as the oxide semiconductor may contain silicon oxide.

Examples of a four-component metal oxide include an In—Sn—Ga—Zn-based oxide, an In—Hf—Ga—Zn-based oxide, an In—Al—Ga—Zn-based oxide, an In—Sn—Al—Zn-based oxide, an In—Sn—Hf—Zn-based oxide, and an In—Hf—Al—Zn-based oxide.

Examples of a three-component metal oxide include an In—Ga—Zn-based oxide (also referred to as IGZO), an In—Sn—Zn-based oxide, an In—Al—Zn-based oxide, Sn—Ga—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, an In—Hf—Zn-based oxide, an In—La—Zn-based oxide, an In—Ce—Zn-based oxide, an In—Pr—Zn-based oxide, an In—Nd—Zn-based oxide, an In—Sm—Zn-based oxide, an In—Eu—Zn-based oxide, an In—Gd—Zn-based oxide, an In—Tb—Zn-based oxide, an In—Dy—Zn-based oxide, an In—Ho—Zn-based oxide, an In—Er—Zn-based oxide, an In—Tm—Zn-based oxide, an In—Yb—Zn-based oxide, and an In—Lu—Zn-based oxide.

Examples of a two-component metal oxide include an In—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, an In—Sn-based oxide, and an In—Ga-based oxide.

Note that for example, an In—Ga—Zn-based oxide refers to an oxide containing In, Ga, and Zn, and there is no limitation on the composition ratio of In, Ga, and Zn. The In—Ga—Zn-based oxide may contain a metal element other than In, Ga, and Zn.

As the oxide semiconductor, a material represented by InLO₃(ZnO)_(m) (m is larger than 0) can be used. Here, L in InLO₃(ZnO)_(m) represents one or more metal elements selected from Ga, Al, Mn, and Co.

As the oxide semiconductor, an In—Ga—Zn-based oxide with an atomic ratio of In:Ga:Zn=1:1:1 (=1/3:1/3:1/3) or In:Ga:Zn=2:2:1 (=2/5:2/5:1/5), or any of oxides whose composition is in the neighborhood of the above compositions can be used. Moreover, as the oxide semiconductor, an In—Sn—Zn-based oxide with an atomic ratio of In:Sn:Zn=1:1:1 (=1/3:1/3:1/3), In:Sn:Zn=2:1:3 (=1/3:1/6:1/2), or In:Sn:Zn=2:1:5 (=1/4:1/8:5/8) or any of oxides whose composition is in the neighborhood of the above compositions can be used.

Without limitation to the materials given above, a material with an appropriate composition can be used depending on required semiconductor characteristics (e.g., mobility, threshold voltage, and variation). In order to obtain the required semiconductor characteristics, it is preferable that the carrier concentration, the impurity concentration, the defect density, the atomic ratio between a metal element and oxygen, the interatomic distance, the density, and the like be set to appropriate values.

The oxide semiconductor may be either single crystal or non-single-crystal. In the latter case, the oxide semiconductor may be either amorphous or polycrystal. Further, the oxide semiconductor may have either an amorphous structure including a portion having crystallinity or a non-amorphous structure.

As the semiconductor layers 603_a and 603_b, it is possible to use a layer of a crystal with c-axis alignment (c-axis aligned crystal (CAAC)), which has a triangular or hexagonal atomic arrangement when seen from the direction of an a-b plane, a surface, or an interface. In the crystal, metal atoms are arranged in a layered manner or metal atoms and oxygen atoms are arranged in a layered manner along the c-axis, and the direction of the a-axis or the b-axis is varied in the a-b plane (the crystal rotates around the c-axis).

The CAAC is not single crystal, but this does not mean that the CAAC is composed of only an amorphous component. Although the CAAC includes a crystallized portion (crystalline portion), a boundary between one crystalline portion and another crystalline portion is not clearly distinguished in some cases.

In the case where oxygen is included in the CAAC, nitrogen may be substituted for part of oxygen included in the CAAC. The c-axes of individual crystalline portions included in the CAAC may be aligned in one direction (e.g., a direction perpendicular to a surface of a substrate over which the CAAC is formed or a surface of the CAAC). Alternatively, the normals of the a-b planes of the individual crystalline portions included in the CAAC may be aligned in one direction (e.g., a direction perpendicular to a surface of a substrate over which the CAAC is formed or a surface of the CAAC).

The CAAC becomes a conductor, a semiconductor, or an insulator depending on its composition or the like. The CAAC transmits or does not transmit visible light depending on its composition or the like.

An example of such a CAAC is a crystal which is formed into a film shape and has a triangular or hexagonal atomic arrangement when observed from the direction perpendicular to a surface of the film or a surface of a substrate, and in which metal atoms are arranged in a layered manner or metal atoms and oxygen atoms (or nitrogen atoms) are arranged in a layered manner when a cross section of the film is observed.

As the oxide semiconductor, it is possible to use a semiconductor material with a composition represented by In_(P)Ga_(Q)O_(R)(ZnO)_(M) (0<P<2, 0<Q<2, and M=1 to 3) as the entire layer including a c-axis-aligned crystalline region with a composition represented by In_(1+σ)Ga_(1−σ)O₃(ZnO) (0<σ<1 and M=1 to 3).

For example, in the case where the semiconductor layers 603_a and 603_b are oxide semiconductor layers containing the CAAC and the channel length of the transistor is 30 nm, a short-channel effect can be prevented even when the semiconductor layers 603_a and 603_b have a thickness of about 5 nm, for instance.

Examples of a crystal structure of the CAAC will be described with reference to FIGS. 8A to 8E, FIGS. 9A to 9C, FIGS. 10A to 10C, and FIGS. 11A and 11B. In FIGS. 8A to 8E, FIGS. 9A to 9C, FIGS. 10A to 10C, and FIGS. 11A and 11B, the vertical direction corresponds to the c-axis direction and a plane perpendicular to the c-axis direction corresponds to the a-b plane, unless otherwise specified. Note that an “upper half” and a “lower half” refer to an upper half above the a-b plane and a lower half below the a-b plane (an upper half and a lower half with respect to the a-b plane). Furthermore, in FIGS. 8A to 8E, O surrounded by a circle represents tetracoordinate O and O surrounded by a double circle represents tricoordinate O.

FIG. 8A illustrates a structure including one hexacoordinate indium (hexacoordinate In) atom and six tetracoordinate oxygen (tetracoordinate O) atoms proximate to the hexacoordinate In atom. Note that a structure including one metal atom such as an In atom and oxygen atoms proximate to the metal atom is referred to as small group. In FIG. 8A, an octahedral structure is illustrated as a planar structure for convenience. Three tetracoordinate O atoms exist in each of the upper and lower halves in FIG. 8A. The electric charge of the small group in FIG. 8A is 0.

FIG. 8B illustrates a structure including one pentacoordinate Ga atom, three tricoordinate oxygen (tricoordinate O) atoms proximate to the pentacoordinate Ga atom, and two tetracoordinate O atoms proximate to the pentacoordinate Ga atom. All the three tricoordinate O atoms exist on the a-b plane. In FIG. 8B, the tetracoordinate O atom exists in each of the upper and lower halves. Since there is a pentacoordinate indium (pentacoordinate In) atom as well as a hexacoordinate In atom, the structure in FIG. 8B can be composed of a pentacoordinate In atom, three tricoordinate O atoms, and two tetracoordinate O atoms. The electric charge of the small group in FIG. 8B is 0.

FIG. 8C illustrates a structure including one tetracoordinate zinc (tetracoordinate Zn) atom and four tetracoordinate O atoms proximate to the tetracoordinate Zn atom. In FIG. 8C, one tetracoordinate O atom exists in the upper half and three tetracoordinate O atoms exist in the lower half. Alternatively, in FIG. 8C, three tetracoordinate O atoms may exist in the upper half and one tetracoordinate O atom may exist in the lower half. The electric charge of the small group in FIG. 8C is 0.

FIG. 8D illustrates a structure including one hexacoordinate tin (hexacoordinate Sn) atom and six tetracoordinate O atoms proximate to the hexacoordinate Sn atom. In FIG. 8D, three tetracoordinate O atoms exist in each of the upper and lower halves. The electric charge of the small group in FIG. 8D is +1.

FIG. 8E illustrates a small group including two zinc atoms. In FIG. 8E, one tetracoordinate O atom exists in each of the upper and lower halves. The electric charge of the small group in FIG. 8E is −1.

Note that a plurality of small groups form a medium group, and a plurality of medium groups form a large group (also referred to as unit cell).

A rule of bonding between the small groups is described below. For example, three tetracoordinate O atoms in the upper half with respect to a hexacoordinate In atom in FIG. 8A are each bonded to three hexacoordinate In atoms which are proximate to and below the tetracoordinate O atom in the upper half, and three tetracoordinate O atoms in the lower half are each bonded to three hexacoordinate In atoms which are proximate to and above the tetra coordinate O atom in the lower half. One tricoordinate O atom in the upper half with respect to a pentacoordinate Ga atom is bonded to one pentacoordinate Ga atom which is proximate to and below the tricoordinate O atom in the upper half, and one tricoordinate O atom in the lower half is bonded to one pentacoordinate Ga atom which is proximate to and above the tricoordinate O atom in the lower half. Moreover, one tetracoordinate O atom in the upper half with respect to a tetracoordinate Zn atom is bonded to one tetracoordinate Zn atom which is proximate to and below the tetracoordinate O atom in the upper half, and three tetracoordinate O atoms in the lower half are each bonded to three tetracoordinate Zn atoms which are proximate to and above the tetracoordinate O atom in the lower half. In this manner, the number of tetracoordinate O atoms above a metal atom is equal to the number of proximate metal atoms below each tetracoordinate O atom. Similarly, the number of tetracoordinate O atoms below a metal atom is equal to the number of proximate metal atoms above each tetracoordinate O atom. Here, since the coordination number of the tetracoordinate O atom is 4, the total number of proximate metal atoms below and above the O atom is 4. Accordingly, when the sum of the number of tetracoordinate O atoms above a metal atom and the number of tetracoordinate O atoms below another metal atom is 4, two kinds of small groups including the metal atoms can be bonded to each other. For example, in the case where a hexacoordinate metal (In or Sn) atom is bonded through three tetracoordinate O atoms in the lower half, it is bonded to a pentacoordinate metal atom or a tetracoordinate metal atom.

A metal atom whose coordination number is 4, 5, or 6 is bonded to another metal atom through a tetracoordinate O atom in the c-axis direction. In addition, a medium group can be formed by combining a plurality of small groups so that the total electric charge of the layered structure is 0.

FIG. 9A illustrates a model of a medium group included in a layered structure of an In—Sn—Zn-based oxide. FIG. 9B illustrates a large group including three medium groups. FIG. 9C illustrates an atomic arrangement where the layered structure shown in FIG. 9B is observed from the c-axis direction.

Note that in FIG. 9A, for convenience, a tricoordinate O atom is omitted and only the number of tetracoordinate O atoms is shown in a circle; for example, three tetracoordinate O atoms existing in each of the upper and lower halves with respect to a Sn atom are denoted by circled 3. Similarly, in FIG. 9A, one tetracoordinate O atom existing in each of the upper and lower halves with respect to an In atom is denoted by circled 1. FIG. 9A also shows a Zn atom proximate to one tetracoordinate O atom in the lower half and three tetracoordinate O atoms in the upper half, and a Zn atom proximate to one tetracoordinate O atom in the upper half and three tetracoordinate O atoms in the lower half.

The medium group included in the layered structure of the In—Sn—Zn-based oxide in FIG. 9A has the following structure. In the order starting from the top, a Sn atom proximate to three tetracoordinate O atoms in each of the upper and lower halves is bonded to an In atom proximate to one tetracoordinate O atom in each of the upper and lower halves; the In atom is bonded to a Zn atom proximate to three tetracoordinate O atoms in the upper half, and is bonded to an In atom proximate to three tetracoordinate O atoms in each of the upper and lower halves through one tetracoordinate O atom in the lower half and the Zn atom; and the In atom is bonded to a small group that includes two Zn atoms and is proximate to one tetracoordinate O atom in the upper half, and is bonded to a Sn atom proximate to three tetracoordinate O atoms in each of the upper and lower halves through one tetracoordinate O atom in the lower half of the small group. A plurality of the medium groups are bonded to form a large group.

Here, electric charge for one bond of a tricoordinate O atom and electric charge for one bond of a tetracoordinate O atom can be assumed to be −0.667 and −0.5, respectively. For example, electric charge of a (hexacoordinate or pentacoordinate) In atom, electric charge of a (tetracoordinate) Zn atom, and electric charge of a (pentacoordinate or hexacoordinate) Sn atom are +3, +2, and +4, respectively. Accordingly, electric charge in a small group including a Sn atom is +1. Therefore, electric charge of −1, by which the electric charge of +1 is canceled, is needed to form a layered structure including a Sn atom. As a structure having electric charge of −1, the small group including two Zn atoms as illustrated in FIG. 8E can be given. For example, with one small group including two Zn atoms, electric charge of one small group including a Sn atom can be cancelled, so that the total electric charge of the layered structure can be 0.

Further, a crystal of an In—Sn—Zn-based oxide (In₂SnZn₃O₈) can be obtained with a structure in which the large group in FIG. 9B is repeated. The layered structure of the In—Sn—Zn-based oxide can be expressed by a composition formula, In₂SnZn₂O₇(ZnO)_(m) (m is 0 or a natural number).

The same can be said for the case of using the other four-component metal oxides, three-component metal oxides, and two-component metal oxides shown in this embodiment and other metal oxides.

As an example, FIG. 10A illustrates a model of a medium group included in a layered structure of an In—Ga—Zn-based oxide.

The medium group included in the layered structure of the In—Ga—Zn-based oxide in FIG. 10A has the following structure. In the order starting from the top, an In atom proximate to three tetracoordinate O atoms in each of the upper and lower halves is bonded to a Zn atom proximate to one tetracoordinate O atom in the upper half; the Zn atom is bonded to a Ga atom proximate to one tetracoordinate O atom in each of the upper and lower halves through three tetracoordinate O atoms in the lower half with respect to the Zn atom; and the Ga atom is bonded to an In atom proximate to three tetracoordinate O atoms in each of the upper and lower halves through one tetracoordinate O atom in the lower half with respect to the Ga atom. A plurality of the medium groups are bonded to form a large group.

FIG. 10B illustrates a large group including three medium groups. FIG. 10C illustrates an atomic arrangement where the layered structure shown in FIG. 10B is observed from the c-axis direction.

Here, since electric charge of a (hexacoordinate or pentacoordinate) In atom, electric charge of a (tetracoordinate) Zn atom, and electric charge of a (pentacoordinate) Ga atom are +3, +2, and +3, respectively, electric charge of a small group including any of the In atom, the Zn atom, and the Ga atom is 0. As a result, the total electric charge of a medium group having a combination of these small groups is always 0.

In order to form the layered structure of the In—Ga—Zn-based oxide, a large group can be formed using not only the medium group in FIG. 10A but also a medium group in which the arrangement of the In atom, the Ga atom, and the Zn atom is different from that in FIG. 10A.

Specifically, when the large group illustrated in FIG. 10B is repeated, a crystal of an In—Ga—Zn-based oxide can be obtained. Note that a layered structure of the In—Ga—Zn-based oxide can be expressed as a composition formula, InGaO₃(ZnO)_(n) (n is a natural number).

In the case of n=1 (InGaZnO₄), a crystal structure illustrated in FIG. 11A can be obtained, for example. Since Ga and In can have five ligands, as described with reference to FIG. 8B, the crystal structure can alternatively be a structure in which Ga in the crystal structure in FIG. 11A is replaced with In.

In the case of n=2 (InGaZn₂O₅), a crystal structure illustrated in FIG. 11B can be obtained, for example. Since Ga and In can have five ligands, as described with reference to FIG. 8B, the crystal structure can alternatively be a structure in which Ga in the crystal structure in FIG. 11B is replaced with In.

The above is the examples of the structure of the CAAC. An oxide semiconductor with crystallinity, such as the CAAC, has fewer defects than an amorphous oxide semiconductor.

The regions 604 a_a, 604 b_a, 604 a_b, and 604 b_b illustrated in FIGS. 7A and 7B are doped with the dopant and function as a source and a drain of the transistor. As the dopant, at least one of elements of Group 13 in the periodic table (e.g., boron), elements of Group 15 in the periodic table (e.g., one or more of nitrogen, phosphorus, and arsenic), and rare gas elements (e.g., one or more of helium, argon, and xenon) can be used, for example. A region functioning as a source of the transistor can be called source region, and a region functioning as a drain of the transistor can be called drain region. Addition of the dopant to the regions 604 a_a, 604 b_a, 604 a_b, and 604 b_b can reduce the resistance between the regions and the conductive layers; thus, the transistor can be downsized.

The conductive layers 605 a_a, 605 b_a, 605 a_b, and 605 b_b function as the source or the drain of the transistor. Note that a layer functioning as a source of the transistor can be called source electrode or source wiring, and a layer functioning as a drain of the transistor can be called drain electrode or drain wiring.

The conductive layers 605 a_a, 605 b_a, 605 a_b, and 605 b_b can be formed using, for example, a layer of a metal material such as aluminum, magnesium, chromium, copper, tantalum, titanium, molybdenum, or tungsten or an alloy material containing any of the above metal materials as a main component. For example, the conductive layers 605 a_a, 605 b_a, 605 a_b, and 605 b_b can be formed using a layer of an alloy material containing copper, magnesium, and aluminum. Moreover, the conductive layers 605 a_a, 605 b_a, 605 a_b, and 605 b_b can be a stack of materials applicable to these conductive layers. For example, the conductive layers 605 a_a, 605 b_a, 605 a_b, and 605 b_b can be formed using a stack including a layer of an alloy material containing copper, magnesium, and aluminum and a layer containing copper.

Alternatively, the conductive layers 605 a_a, 605 b_a, 605 a_b, and 605 b_b can be a layer containing a conductive metal oxide. Examples of the conductive metal oxide include indium oxide, tin oxide, zinc oxide, indium oxide-tin oxide, and indium oxide-zinc oxide. Note that silicon oxide may be contained in the conductive metal oxide applicable to the conductive layers 605 a_a, 605 b_a, 605 a_b, and 605 b_b.

As the insulating layers 606 a and 606 b, a layer of a material applicable to the insulating layers 602_a and 602_b can be used, for example. Alternatively, the insulating layers 606 a and 606 b can be formed using a stack of materials applicable to the insulating layers 606 a and 606 b.

The insulating layer 607 functions as a protective insulating layer for preventing impurities from entering the transistor.

As the insulating layer 607, a layer of a material applicable to the insulating layers 602_a and 602_b can be used, for example. Alternatively, the insulating layer 607 can be formed using a stack of materials applicable to the insulating layer 607. For example, insulating layer 607 may be formed using a silicon oxide layer, an aluminum oxide layer, or the like. For example, the use of an aluminum oxide layer as the insulating layer 607 can more effectively prevent impurities from entering the semiconductor layer 603_b and effectively prevent the semiconductor layer 603_b from releasing oxygen.

Note that the transistor in this embodiment may have a structure in which an insulating layer is provided over part of the oxide semiconductor layer serving as a channel formation layer and a conductive layer serving as a source or a drain is provided to overlap with the oxide semiconductor layer with the insulating layer placed therebetween. In that case, the insulating layer functions as a layer protecting the channel formation layer of the transistor (also referred to as channel protective layer). As the insulating layer functioning as a channel protective layer, a layer containing a material applicable to the insulating layers 602_a and 602_b can be used, for example. Alternatively, the insulating layer functioning as a channel protective layer may be a stack of materials applicable to the insulating layers 602_a and 602_b.

Further, base layers may be formed over the element formation layers 600_a and 600_b and the transistors may be formed over the base layers. In that case, the base layer can be a layer of a material applicable to the insulating layers 602_a and 602_b, for example. Alternatively, the base layer may be a stack of materials applicable to the insulating layers 602_a and 602_b. For example, a stack of an aluminum oxide layer and a silicon oxide layer used as the base layer can prevent oxygen in the base layer from being released through the semiconductor layers 603_a and 603_b.

Next, as an example of a method of manufacturing the transistor in this embodiment, an example of a method of manufacturing the transistor in FIG. 7A will be described with reference to FIGS. 12A to 12E. FIGS. 12A to 12E are schematic cross-sectional views illustrating a method of manufacturing the transistor in FIG. 7A.

First, as illustrated in FIG. 12A, the element formation layer 600_a is prepared, and the semiconductor layer 603_a is formed over the element formation layer 600_a.

For example, a film of an oxide semiconductor material applicable to the semiconductor layer 603_a (such a film is also referred to as oxide semiconductor film) is formed by sputtering, thereby forming the semiconductor layer 603_a. Note that the oxide semiconductor film may be partly etched after the deposition. Moreover, the oxide semiconductor film may be formed in a rare gas atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen.

The oxide semiconductor film may be formed using, as a sputtering target, an oxide target having a composition ratio of In:Ga:Zn=1:1:1, 4:2:3, 3:1:2, 1:1:2, 2:1:3, or 3:1:4 (in an atomic ratio). The oxide target having any of the above composition ratios enables formation of a highly crystalline oxide semiconductor film, and facilitates formation of polycrystals or CAAC's.

In addition, the oxide semiconductor film may be formed using, as the sputtering target, an oxide target having a composition ratio of In:Sn:Zn=1:2:2, 2:1:3, 1:1:1, or 20:45:35 (in an atomic ratio). The oxide target having any of the above composition ratios enables formation of a highly crystalline oxide semiconductor film, and facilitates formation of polycrystals or CAAC's.

Furthermore, an In—Zn-based oxide film may be formed using, as the sputtering target, an oxide target having a composition ratio of In:Zn=50:1 to 1:2 (In₂O₃:ZnO=25:1 to 1:4 in a molar ratio), preferably In:Zn=20:1 to 1:1 (In₂O₃:ZnO=10:1 to 1:2 in a molar ratio), further preferably In:Zn=15:1 to 1.5:1 (In₂O₃:ZnO=15:2 to 3:4 in a molar ratio). Furthermore, when the atomic ratio of the target used for forming the In—Zn-based oxide semiconductor film is expressed by In:Zn:O=S:U:R, R>1.5S+U is satisfied. The increase in In content makes the field-effect mobility (also simply referred to as mobility) of the transistor higher.

In the case of using a sputtering method, the semiconductor layer 603_a is formed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen, for example. In that case, when the semiconductor layer 603_a is formed in a mixed atmosphere of a rare gas and oxygen, the oxygen content is preferably higher than the rare gas content.

When the film is formed by sputtering, it is preferable to sufficiently suppress leakage from the outside of a deposition chamber and degasification through an inner wall of the deposition chamber so that impurities such as hydrogen, water, a hydroxyl group, or hydride (also referred to as hydrogen compound) are not included in a deposited film.

For example, before the film is formed by sputtering, preheat treatment may be performed in a preheating chamber of a sputtering apparatus. By the preheat treatment, the above impurities can be eliminated.

Before the film is formed by sputtering, for example, it is possible to perform treatment by which voltage is applied to a substrate side, not to a target side, in an argon, nitrogen, helium, or oxygen atmosphere with the use of an RF power source and plasma is generated so that a surface of the substrate on which the film is to be formed is modified (such treatment is also referred to as reverse sputtering). With reverse sputtering, powdery substances (also referred to as particles or dust) attached to the surface where the film is to be formed can be removed.

In the case where the film is formed by sputtering, moisture remaining in the deposition chamber for forming the film can be removed by an entrapment vacuum pump or the like. As the entrapment vacuum pump, a cryopump, an ion pump, or a titanium sublimation pump can be used, for example. Alternatively, moisture remaining in the deposition chamber can be removed by a turbo molecular pump provided with a cold trap. With the use of the vacuum pump, back flow of the exhaust including the impurities can be reduced.

When a high-purity gas from which the above impurities are removed is used as a sputtering gas, for example, the impurity concentration of the deposited film can be lowered. For instance, a gas with a dew point of −70° C. or lower is preferably used as a sputtering gas.

The oxide semiconductor film may alternatively be formed by, instead of a sputtering method, a vacuum evaporation method, a plasma-enhanced chemical vapor deposition (PECVD) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, a molecular beam epitaxy (MBE) method, or the like.

In the example of the method of manufacturing the transistor in this embodiment, a layer is formed by etching part of a film in the following manner, for instance: a resist mask is formed over part of the film by a photolithography process and the film is etched using the resist mask, thereby forming the layer. Note that in this case, the resist mask is removed after the layer is formed.

When an oxide semiconductor layer containing the CAAC is formed as the semiconductor layer 603_a, the oxide semiconductor film is formed by sputtering while the temperature of the element formation layer where the oxide semiconductor film is formed ranges from 100° C. to 600° C., preferably from 150° C. to 550° C., more preferably from 200° C. to 500° C. The oxide semiconductor film is deposited while the temperature of the element formation layer is high, whereby the impurity concentration in the film is reduced, the field-effect mobility of the transistor to be manufactured can be increased, and the gate-bias stress stability can be increased. Further, the atomic arrangement in the oxide semiconductor film is ordered, the density thereof is increased, so that a polycrystal or a CAAC is easily formed. Furthermore, a polycrystal or CAAC is also more easily formed by film deposition in an oxygen gas atmosphere because an unnecessary atom such as a rare gas does not enter the film. Note that a mixed gas atmosphere including an oxygen gas and a rare gas may be used. In that case, the percentage of an oxygen gas is higher than or equal to 30 vol. %, preferably higher than or equal to 50 vol. %, more preferably higher than or equal to 80 vol. %. As the oxide semiconductor film is thinner, the short channel effect of the transistor can be reduced.

Here, the thickness of the oxide semiconductor layer ranges from 1 nm to 40 nm, preferably from 3 nm to 20 nm.

In that case, the element formation layer 600_a is preferably flat. For example, the average surface roughness of the element formation layer 600_a is preferably 1 nm or less, further preferably 0.3 nm or less. By making the element formation layer 600_a flatter, the mobility of the CAAC oxide semiconductor can be made higher than that of an amorphous oxide semiconductor. For example, the element formation layer 600_a can be flattened by at least one of chemical mechanical polishing (CMP) and plasma treatment. Here, plasma treatment includes treatment for performing sputtering on a surface with rare gas ions and treatment for performing etching on a surface with an etching gas.

Then, as illustrated in FIG. 12B, the conductive layers 605 a_a and 605 b_a are formed over the semiconductor layer 603_a.

For example, a film of a material applicable to the conductive layers 605 a_a and 605 b_a is formed as a first conductive film by sputtering, and the first conductive film is partly etched, thereby forming the conductive layers 605 a_a and 605 b_a.

Next, as illustrated in FIG. 12C, the insulating layer 602_a is formed in contact with the semiconductor layer 603_a.

For example, the insulating layer 602_a can be formed by depositing a film applicable to the insulating layer 602_a by sputtering in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen. The temperature of the element formation layer 600_a at the time when the insulating layer 602_a is formed preferably ranges from room temperature to 300° C.

Before the formation of the insulating layer 602_a, plasma treatment with the use of a gas such as N₂O, N₂, or Ar may be performed to remove water or the like adsorbed on an exposed surface of the semiconductor layer 603_a. In the case where the plasma treatment is performed, the insulating layer 602_a is preferably formed after the plasma treatment without exposure to air.

Next, the conductive layer 601_a is formed over the insulating layer 602_a.

For example, a film of a material applicable to the conductive layer 601_a is formed as a second conductive film by sputtering, and the second conductive film is partly etched, thereby forming the conductive layer 601_a.

Further, in the example of the method of manufacturing the transistor in FIG. 7A, heat treatment is performed, for example, at higher than or equal to 600° C. and lower than or equal to 750° C., or higher than or equal to 600° C. and lower than the strain point of the substrate. For example, the heat treatment is performed after the oxide semiconductor film is formed, after the oxide semiconductor film is partly etched, after the first conductive film is formed, after the first conductive film is partly etched, after the insulating layer 602_a is formed, after the second conductive film is formed, or after the second conductive film is partly etched. The heat treatment eliminates impurities such as hydrogen, water, a hydroxyl group, or hydride from the semiconductor layer 603_a.

Note that a heat treatment apparatus for the heat treatment can be an electric furnace or an apparatus for heating an object by heat conduction or heat radiation from a heater such as a resistance heater. For example, a rapid thermal annealing (RTA) apparatus such as a gas rapid thermal annealing (GRTA) apparatus or a lamp rapid thermal annealing (LRTA) apparatus can be used. An LRTA apparatus is an apparatus for heating an object by radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. A GRTA apparatus is an apparatus for heat treatment using a high-temperature gas. As the high-temperature gas, a rare gas or an inert gas (e.g., nitrogen) which does not react with the object by the heat treatment can be used.

Further, after the heat treatment is performed and while the heating temperature is being maintained or being decreased, a high-purity oxygen gas, a high-purity N₂O gas, or ultra-dry air (having a dew point −40° C. or lower, preferably −60° C. or lower) may be introduced in the furnace where the heat treatment has been performed. It is preferable that the oxygen gas or the N₂O gas do not contain water, hydrogen, and the like. The purity of the oxygen gas or the N₂O gas which is introduced into the heat treatment apparatus is preferably 6N or higher, further preferably 7N or higher; that is, the impurity concentration of the oxygen gas or the N₂O gas is preferably 1 ppm or lower, further preferably 0.1 ppm or lower. By the action of the oxygen gas or the N₂O gas, oxygen is supplied to the semiconductor layer 603_a, and defects due to oxygen vacancy in the semiconductor layer 603_a can be reduced. Note that the high-purity oxygen gas, high-purity N₂O gas, or ultra-dry air may be introduced during the heat treatment.

In the example of the method of manufacturing the transistor in FIG. 7A, oxygen may be implanted into the oxide semiconductor film with a method of accelerating oxygen ions by electric fields, such as oxygen doping using oxygen plasma, after the semiconductor layer 603_a is formed, after the conductive layers 605 a_a and 605 b_a are formed, after the insulating layer 602_a is formed, after the conductive layer 601_a is formed, or after the heat treatment is performed. For example, oxygen doping using a high-density plasma of 2.45 GHz may be performed. Alternatively, oxygen doping may be performed by an ion implantation method. The oxygen doping can reduce variations in electrical characteristics of transistors to be manufactured. For example, the oxygen doping is performed so that the insulating layer 602_a contains oxygen with a higher proportion than that in the stoichiometric composition.

When the insulating layer in contact with the semiconductor layer 603_a contains an excessive amount of oxygen, oxygen is easily supplied to the semiconductor layer 603_a. Thus, oxygen defects in the semiconductor layer 603_a or at the interface between the insulating layer 602_a and the semiconductor layer 603_a can be reduced, which results in further reduction in the carrier concentration of the semiconductor layer 603_a. This embodiment is not limited to the above; even if an excessive amount of oxygen is contained in the semiconductor layer 603_a through the manufacturing process, the insulating layer in contact with the semiconductor layer 603_a can prevent oxygen from being released from the semiconductor layer 603_a.

For example, when an insulating layer containing gallium oxide is formed as the insulating layer 602_a, the composition of gallium oxide can be set to be Ga₂O_(x) by supplying the insulating layer with oxygen.

When an insulating layer containing aluminum oxide is formed as the insulating layer 602_a, the composition of aluminum oxide can be set to be Al₂O_(x) by supplying the insulating layer with oxygen.

Further, when an insulating layer containing gallium aluminum oxide or aluminum gallium oxide is formed as the insulating layer 602_a, the composition of gallium aluminum oxide or aluminum gallium oxide can be set to be Ga_(x)Al_(2−x)O_(3+α) by supplying the insulating layer with oxygen.

Through the above steps, impurities such as hydrogen, water, a hydroxyl group, or hydride (hydrogen compound) are removed from the semiconductor layer 603_a and oxygen is supplied to the semiconductor layer 603_a; thus, the oxide semiconductor layer can be highly purified.

In addition to the heat treatment, after the insulating layer 602_a is formed, heat treatment (preferably at 200° C. to 600° C., for example, at 250° C. to 350° C.) may be performed in an inert gas atmosphere or an oxygen gas atmosphere.

The intended heating temperature of the element formation layer 600_a or the temperature of the heat treatment after the deposition of the oxide semiconductor film is 150° C. or higher, preferably 200° C. or higher, further preferably 400° C. or higher. When the heat treatment after the oxide semiconductor film is deposited is performed at 300° C. or higher, impurities such as hydrogen contained in the film can be released and removed (the film can be dehydrated or dehydrogenated).

The heat treatment can be performed in an oxygen atmosphere; alternatively, the following two steps may be performed: the above dehydration or dehydrogenation is performed under a nitrogen atmosphere or a reduced pressure and then thermal treatment is performed in an oxygen atmosphere. By performing thermal treatment in an atmosphere including oxygen after the dehydration or dehydrogenation, oxygen can be added to the oxide semiconductor, so that the effect of the heat treatment can be further enhanced. Moreover, as the treatment for supplying oxygen, thermal treatment may be performed while the insulating layer is placed in contact with the oxide semiconductor layer. A defect due to oxygen vacancy is easily caused in the oxide semiconductor layer or at the interface between the oxide semiconductor layer and a layer stacked over the oxide semiconductor layer, for example; however, when excess oxygen is included in the oxide semiconductor by the heat treatment, oxygen vacancy caused constantly can be compensated for by excess oxygen. The excess oxygen is mainly oxygen existing between lattices. By setting the concentration of oxygen in the range of 1×10¹⁶/cm³ to 2×10²⁰/cm³, oxygen can be included in the oxide semiconductor layer without causing crystal distortion or the like even if the oxide semiconductor layer is crystallized, for example.

The heat treatment performed after the formation of the oxide semiconductor film can increase the gate-bias stress stability of the transistor to be manufactured, and can increase the field-effect mobility of the transistor.

Then, as illustrated in FIG. 12E, a dopant is added to the semiconductor layer 603_a from a side on which the conductive layer 601_a is formed, so that the region 604 a_a and the region 604 b_a are formed in a self-aligned manner through the insulating layer 602_a.

For example, the dopant can be added by an ion doping apparatus or an ion implantation apparatus.

Note that the given example of the method of manufacturing the transistor is not necessarily applied only to the transistor in FIG. 7A. For example, the above description of the example of the method of manufacturing the transistor in FIG. 7A can be applied as appropriate to the components in FIG. 7B which have the same designations as the components in FIG. 7A and have a function at least partly the same as that of the components in FIG. 7A.

As described with reference to FIGS. 7A and 7B, FIGS. 8A to 8E, FIGS. 9A to 9C, FIGS. 10A to 10C, FIGS. 11A and 11B, and FIGS. 12A to 12E, each example of the transistor in this embodiment includes a conductive layer functioning as a gate; an insulating layer functioning as a gate insulating layer; an oxide semiconductor layer in which a channel is formed and which overlaps with the conductive layer functioning as the gate with the insulating layer functioning as the gate insulating layer placed therebetween; a conductive layer that is electrically connected to the oxide semiconductor layer and functions as one of a source and a drain; and a conductive layer that is electrically connected to the oxide semiconductor layer and functions as the other of the source and the drain.

In the transistor in the example of this embodiment, the carrier concentration of the oxide semiconductor layer can be lower than 1×10¹⁴/cm³, preferably lower than 1×10¹²/cm³, more preferably lower than 1×10¹¹/cm³.

The carrier concentration of an oxide semiconductor applied to the transistor is preferably 10¹⁸/cm³ or lower. An oxide semiconductor containing In or Zn can have a carrier concentration of 10¹⁸/cm³ or lower by performing high purification of the oxide semiconductor film (removal of hydrogen and the like) or heat treatment after the deposition as described above, as well as by containing Ga or Sn as its component.

By performing at least one of the heat treatment during the deposition of the oxide semiconductor film and the heat treatment after the deposition, the threshold voltage of the transistor can be positively shifted to make the transistor normally off, and the off-state current per micrometer of channel width can be 10 aA (1×10⁻¹⁷ A) or less, 1 aA (1×10⁻¹⁸ A) or less, 10 zA (1×10⁻²⁰ A) or less, 1 zA (1×10⁻²¹ A) or less, and even 100 yA (1×10⁻²² A) or less. It is preferable that the off-state current of the transistor be as low as possible; the lower limit of the off-state current of the transistor in this embodiment is estimated to be about 10⁻³⁰ A/μm.

With the use of the transistor including the oxide semiconductor layer in this embodiment as the transistor for controlling the potential of the output signal in any of the arithmetic circuit in the above embodiments for example, a data retention period of the arithmetic circuit can be prolonged.

The transistor in the example of this embodiment and another transistor, for example, a transistor including a semiconductor layer containing a semiconductor belonging to Group 14 of the periodic table (e.g., silicon) can be stacked. Thus, the circuit area can be reduced while the transistor including the oxide semiconductor layer and the another transistor can be formed over one substrate.

The transistor including the oxide semiconductor can have relatively high field-effect mobility regardless of whether the oxide semiconductor is amorphous or crystalline. Such an increase in field-effect mobility might be attributed not only to removal of impurities by dehydration or dehydrogenation but also to a reduction in interatomic distance due to an increase in density. Moreover, the oxide semiconductor film can be crystallized by being purified by removal of impurities from the oxide semiconductor film. For example, the field-effect mobility of a transistor including an In—Sn—Zn-based oxide semiconductor can be higher than 31 cm²/V·s, preferably higher than 39 cm²/V·s, further preferably higher than 60 cm²/V·s. It has been proposed that ideally, a highly purified non-single-crystal oxide semiconductor can achieve a field-effect mobility exceeding 100 cm²/V·s. In addition, the example of the transistor in this embodiment indicates that the field-effect mobility thereof is increased as the defect density of the oxide semiconductor layer decreases. The reason therefor will be given below.

The actually measured field-effect mobility of a field-effect transistor, which is not limited to one including an oxide semiconductor layer, is lower than its inherent mobility for a variety of reasons. One of causes for reduction in the field-effect mobility is a defect in a semiconductor layer or a defect at an interface between the semiconductor layer and an insulating layer. For example, with a Levinson model, the field-effect mobility of a transistor based on the assumption that no defect exists inside an oxide semiconductor layer can be calculated theoretically.

Assuming a potential barrier (such as a grain boundary) exists in a semiconductor layer, the measured field-effect mobility of the semiconductor layer, denoted by is expressed by Formula 1 where the inherent field-effect mobility of the semiconductor layer is μ₀.

$\begin{matrix} {\left\lbrack {{FORMULA}\mspace{14mu} 1} \right\rbrack\mspace{585mu}} & \; \\ {\mu = {\mu_{0}{\exp\left( {- \frac{E}{kT}} \right)}}} & (1) \end{matrix}$

In Formula 1, E denotes the height of the potential barrier, k denotes the Boltzmann constant, and T denotes the absolute temperature. Further, on the assumption that the potential barrier is attributed to a defect, the height of the potential barrier E can be expressed by Formula 2 according to the Levinson model.

$\begin{matrix} {\left\lbrack {{FORMULA}\mspace{14mu} 2} \right\rbrack\mspace{585mu}} & \; \\ {E = {\frac{e^{2}N^{2}}{8ɛ\; n} = \frac{e^{2}N^{2}t}{8ɛ\;{CoxVg}}}} & (2) \end{matrix}$

In Formula 2, e denotes the elementary charge, N denotes the average defect density per unit area in a channel, ε denotes the permittivity of the semiconductor, n denotes the carrier concentration per unit area in the channel, C_(ox) denotes the capacitance per unit area, V_(g) denotes the gate voltage (voltage between a gate and a source), and t denotes the thickness of the channel. In the case where the thickness of the semiconductor layer is less than or equal to 30 nm, the thickness of the channel can be regarded as being the same as the thickness of the semiconductor layer. In addition, the drain current I_(d) (current between a drain and the source) in a linear region is expressed by Formula 3.

$\begin{matrix} {\left\lbrack {{FORMULA}\mspace{14mu} 3} \right\rbrack\mspace{585mu}} & \; \\ {{Id} = {\frac{W\;\mu\;{VgVdCox}}{L}{\exp\left( {- \frac{E}{kT}} \right)}}} & (3) \end{matrix}$

In Formula 3, L denotes the channel length and W denotes the channel width, and L and Ware each 10 μm in this example. Moreover, V_(d) denotes the drain voltage. Both sides of Formula 3 are divided by V_(g) and then logarithms of both the sides are taken, resulting in Formula 4.

$\begin{matrix} {\left\lbrack {{FORMULA}\mspace{14mu} 4} \right\rbrack\mspace{585mu}} & \; \\ {{\ln\left( \frac{Id}{Vg} \right)} = {{{\ln\left( \frac{W\;\mu\;{VdCox}}{L} \right)} - \frac{E}{kT}} = {{\ln\left( \frac{W\;\mu\;{VdCox}}{L} \right)} - \frac{e^{3}N^{2}t}{8\;{kT}\; ɛ\;{CoxVg}}}}} & (4) \end{matrix}$

The right side of Formula 4 is a function of V_(g). From Formula 4, it is found that the defect density N can be obtained from a line in a graph that is obtained by plotting actual measured values with ln(I_(d)/V_(g)) as the ordinate and 1/V_(g) as the abscissa. That is, the defect density can be evaluated from the I_(d)−V_(g) characteristics of the transistor. For example, the defect density N of an oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn) in a 1:1:1 atomic ratio is about 1×10¹²/cm².

On the basis of the defect density or the like obtained in the above manner, μ₀, the inherent field-effect mobility of the oxide semiconductor layer, is calculated to be 120 cm²/V·s. In general, the measured field-effect mobility of an In—Ga—Zn-based oxide having a defect is about 40 cm²/V·s; however, assuming that no defect exists inside the oxide semiconductor and at the interface between the oxide semiconductor and an insulating film, the mobility μ₀ of the oxide semiconductor is expected to be 120 cm²/V·s. It is thus found that the mobility of the oxide semiconductor and the field-effect mobility of the transistor are increased as defects are decreased. For example, an oxide semiconductor layer containing the CAAC or the like has low defect density.

Note that even when no defect exists inside the semiconductor layer, scattering at an interface between a channel and a gate insulating layer affects the transport property of the transistor. In other words, the mobility μ₁ at a position that is a distance x away from the interface between the channel and the gate insulator is expressed by Formula 5.

$\begin{matrix} {\left\lbrack {{FORMULA}\mspace{14mu} 5} \right\rbrack\mspace{585mu}} & \; \\ {\frac{1}{\mu_{1}} = {\frac{1}{\mu_{0}} + {\frac{D}{B}{\exp\left( {- \frac{x}{l}} \right)}}}} & (5) \end{matrix}$

In Formula 5, D denotes the electric field in the gate direction, and B and l are constants. The values of B and l can be obtained from actual measurement results; according to the above measurement results, B is 2.38×10⁷ cm/s and l is 10 nm (the depth to which the influence of interface scattering reaches). In Formula 5, the second term is increased as D increases (i.e., as the gate voltage increases); accordingly, the mobility μ₁ is decreased as D increases.

FIG. 13 shows calculation results of the mobility μ₂ of a transistor whose channel is formed in an ideal oxide semiconductor layer with no defect therein. For the calculation, Sentaurus Device, the software manufactured by Synopsys, Inc., is used. For the calculation, the band gap, the electron affinity, the relative permittivity, and the thickness of the oxide semiconductor layer are 2.8 eV, 4.7 eV, 15, and 15 nm, respectively. The work functions of a gate, a source, and a drain of the transistor are 5.5 eV, 4.6 eV, and 4.6 eV, respectively. The thickness of a gate insulating layer is 100 nm, and the relative permittivity thereof is 4.1. The channel length and the channel width of the transistor are each 10 μm, and the drain voltage V_(d) is 0.1 V.

As shown in FIG. 13, the field-effect mobility is as high as 100 cm²/V·s or more at a gate voltage V_(g) around 1 V, and decreases as the gate voltage V_(g) becomes higher because the influence of interface scattering is increased. In order to reduce interface scattering, it is preferable that a surface of the semiconductor layer be flat at the atomic level (i.e., atomic layer flatness).

The following shows the calculation results of electrical characteristics of a minute transistor using an oxide semiconductor having the above-described high field-effect mobility.

FIGS. 14A and 14B show cross-sectional structures of transistors used for the calculation. The transistors illustrated in FIGS. 14A and 14B each include n-type semiconductor regions 653 a and 653 b and a semiconductor region 653 c in an oxide semiconductor layer. The resistivity of the semiconductor regions 653 a and 653 b is 2×10⁻³ Ω·cm.

The transistor in FIG. 14A is provided over a base insulator 651 and a buried insulator 652. The buried insulator 652 is formed using aluminum oxide and provided to be embedded in the base insulator 651. The buried insulator 652 allows oxygen to be easily supplied to the semiconductor region 653 c.

The transistor in FIG. 14A includes the semiconductor region 653 a, the semiconductor region 653 b, the semiconductor region 653 c, a gate insulating layer 654, a gate electrode 655, a sidewall insulator 656 a, a sidewall insulator 656 b, an insulating layer 657, a source electrode 658 a, and a drain electrode 658 b.

The semiconductor region 653 c is positioned between the semiconductor region 653 a and the semiconductor region 653 b. The semiconductor region 653 c is an intrinsic semiconductor region serving as a channel formation region.

The gate electrode 655 is provided over the gate insulating layer 654. The width of the gate electrode 655 is 33 nm.

The sidewall insulators 656 a and 656 b are provided in contact with side surfaces of the gate electrode 655. In the transistor in FIG. 14A, a semiconductor region below the sidewall insulator 656 a is included in the n-type semiconductor region 653 a, and a semiconductor region below the sidewall insulator 656 b is included in the n-type semiconductor region 653 b. The width of the sidewall insulators 656 a and 656 b is 5 nm.

The insulating layer 657 is provided over the gate electrode 655. The insulating layer 657 has a function of preventing a short circuit between the gate electrode 655 and a wiring.

The source electrode 658 a is in contact with the semiconductor region 653 a.

The drain electrode 658 b is in contact with the semiconductor region 653 b.

Note that the channel width of the transistor in FIG. 14A is 33 nm.

The transistor in FIG. 14B differs from the transistor in FIG. 14A in the conductivity type of the semiconductor regions below the sidewall insulators 656 a and 656 b. In the transistor in FIG. 14B, the semiconductor regions below the sidewall insulators 656 a and 656 b are included in the intrinsic semiconductor region 653 c. In other words, the transistor in FIG. 14B includes regions where the semiconductor region 653 a and the gate electrode 655 do not overlap with each other and the semiconductor region 653 c and the gate electrode 655 do not overlap with each other. These regions are called offset regions, and their width is called offset length (L_(off)). In FIG. 14B, the offset length is the same as the width of the sidewall insulators 656 a and 656 b.

Note that the other parameters used in calculation are as described above. For the calculation, Sentaurus Device, the software manufactured by Synopsys, Inc., is used.

FIGS. 15A to 15C show the gate voltage (V_(g): a potential difference between the gate and the source) dependence of the drain current I_(d) (indicated by a solid line) and the field-effect mobility μ (indicted by a dotted line) of the transistor having the structure in FIG. 14A. The drain current I_(d) is calculated under the assumption that the drain voltage V_(d) (potential difference between the drain and the source) is +1 V, and the field-effect mobility μ is calculated under the assumption that the drain voltage is +0.1 V.

FIG. 15A shows the gate voltage dependence of the transistor including the gate insulating layer 654 with a thickness of 15 nm. FIG. 15B shows the gate voltage dependence of the transistor including the gate insulating layer 654 with a thickness of 10 nm FIG. 15C shows the gate voltage dependence of the transistor including the gate insulating layer 654 with a thickness of 5 nm. As shown in FIGS. 15A to 15C, as the gate insulating layer 654 is thinner, the drain current I_(d) in the off state (off-state current) in particular is significantly decreased. In contrast, there is no remarkable tendency in the peak value of the field-effect mobility μ and the drain current I_(d) in the on state (on-state current). Further, the drain current exceeds 10 μA, which is needed in a storage circuit and the like, at a gate voltage around 1 V.

FIGS. 16A to 16C show the gate voltage dependence of the drain current I_(d) (solid line) and the mobility (dotted line) of the transistor that has the structure in FIG. 14B and has an offset length (L_(off)) of 5 nm. Here, the drain current I_(d) is calculated on the assumption the drain voltage V_(d) is +1 V, and the field-effect mobility μ is calculated on the assumption the drain voltage V_(d) is +0.1 V. FIG. 16A shows the gate voltage dependence of the transistor including the gate insulating layer 654 with a thickness of 15 nm FIG. 16B shows the gate voltage dependence of the transistor including the gate insulating layer 654 with a thickness of 10 nm. FIG. 16C shows the gate voltage dependence of the transistor including the gate insulating layer 654 with a thickness of 5 nm.

FIGS. 17A to 17C show the gate voltage dependence of the drain current I_(d) (solid line) and the mobility (dotted line) of the transistor that has the structure in FIG. 14B and has an offset length (L_(off)) of 15 nm. Here, the drain current I_(d) is calculated on the assumption the drain voltage V_(d) is +1 V, and the mobility μ is calculated on the assumption the drain voltage V_(d) is +0.1 V. FIG. 17A shows the gate voltage dependence of the transistor including the gate insulating layer 654 with a thickness of 15 nm. FIG. 17B shows the gate voltage dependence of the transistor including the gate insulating layer 654 with a thickness of 10 nm. FIG. 17C shows the gate voltage dependence of the transistor including the gate insulating layer 654 with a thickness of 5 nm.

As seen from FIGS. 15A to 15C, FIGS. 16A to 16C, and FIGS. 17A to 17C, as the gate insulating layer 654 is thinner in any of the structures, the off-state current of the transistor is significantly decreased, whereas there is no remarkable change tendency in the peak value of the mobility μ and the on-state current of the transistor.

The peak of the field-effect mobility μ is about 80 cm²/V·s in FIGS. 15A to 15C, about 60 cm²/V·s in FIGS. 16A to 16C, and about 40 cm²/V·s in FIGS. 17A to 17C; thus, the peak of the mobility μ decreases as the offset length (L_(off)) is increased. The same applies to the off-state current of the transistor. The on-state current of the transistor also decreases as the offset length (L_(off)) is increased; however, the decrease in the on-state current is much more gradual than the decrease in the off-state current of the transistor. Further, the drain current exceeds 10 μA, which is needed for a storage circuit and the like, at a gate voltage around 1 V.

Since the field-effect mobility of the transistor including an oxide semiconductor can be high as described above, the transistor can operate the arithmetic circuit in any of the above embodiments without problems.

Next, as another example of the transistor, an example of a transistor that includes an oxide semiconductor layer containing In, Sn, and Zn as a channel formation layer will be described.

FIGS. 18A to 18C show characteristics of a transistor that includes an oxide semiconductor layer containing In, Sn, and Zn as its main components and a 100-nm-thick gate insulating layer, and has a channel length L of 3 μm and a channel width W of 10 μm. Note that V_(d) is 10V.

FIG. 18A shows characteristics of a transistor in which an oxide semiconductor layer is formed by deposition of an oxide semiconductor film containing In, Sn, and Zn as its main components by sputtering without heating an element formation layer intentionally. FIG. 18A shows that the field-effect mobility is 18.8 cm²/V·s. FIG. 18B shows characteristics of a transistor in which an oxide semiconductor layer is formed by deposition of an oxide semiconductor film containing In, Sn, and Zn as its main components by sputtering while a substrate is heated at 200° C. FIG. 18B shows that the field-effect mobility is 32.2 cm²/V·s. This means that intentional heating increases the field-effect mobility of the transistor.

FIG. 18C shows characteristics of a transistor in which an oxide semiconductor layer is formed by deposition of an oxide semiconductor film containing In, Sn, and Zn as its main components by sputtering at 200° C. and then subjected to heat treatment at 650° C. FIG. 18C shows that the field-effect mobility is 34.5 cm²/V·s. This means that heat treatment performed after the oxide semiconductor film is deposited increases the field-effect mobility.

Note that the oxide semiconductor layer containing In, Sn, and Zn as its main components may be crystallized in the following manner: oxygen ions are implanted into the oxide semiconductor layer, impurities such as hydrogen, water, a hydroxyl group, or hydride included in the oxide semiconductor are released by heat treatment, and the oxide semiconductor layer is crystallized through the heat treatment or by another heat treatment performed later. By such crystallization treatment or recrystallization treatment, a non-single-crystal oxide semiconductor layer with favorable crystallinity can be obtained.

As for the transistor including the oxide semiconductor layer that contains In, Sn, and Zn as its main components and is formed without heating the element formation layer intentionally, the threshold voltage tends to be negative as shown in FIG. 18A, for example. In contrast, as for the transistor including the oxide semiconductor layer that is formed while the element formation layer is intentionally heated, the threshold voltage is higher than that in the case where the element formation layer is not heated, so that the transistor can be close to a normally-off transistor as shown in FIG. 18B, for example. It is thus found that at least one of the heat treatment during the deposition of the oxide semiconductor film and the heat treatment after the deposition makes the transistor more likely to be normally off.

The threshold voltage of a transistor can also be controlled by changing the ratio of In, Sn, and Zn. For example, when the composition ratio of In, Sn, and Zn in the oxide semiconductor film is 2:1:3, the transistor is more likely to be normally off.

For example, when a gate bias is applied with an intensity of 2 MV/cm at 150° C. for 1 hour to perform a bias-temperature stress test (BT test), the drift of the threshold voltage is less than ±1.5 V, preferably less than ±1.0 V. This means that the stability against gate-bias stress is enhanced by at least one of the heat treatment during the deposition of the oxide semiconductor film and the heat treatment after the deposition. FIGS. 19A and 19B and FIGS. 20A and 20B show the results of the BT test performed on the following two transistors: Sample 1 on which heat treatment is not performed after formation of an oxide semiconductor film, and Sample 2 on which heat treatment at 650° C. is performed after formation of an oxide semiconductor film. As the BT test, a positive BT test and a negative BT test were performed.

In the positive BT test, first, V_(g)−I_(d) characteristics of the transistors were measured at a temperature of element formation layers (substrates) of 25° C. and V_(d) of 10 V. Then, the temperature of the element formation layers (substrates) was set to 150° C. and V_(d) was set to 0.1 V. After that, V_(g) of 20 V was applied so that the intensity of an electric field applied to gate insulating layers was 2 MV/cm, and the condition was kept for 1 hour. Next, V_(g) was set to 0 V. Then, V_(g)−I_(d) characteristics of the transistors were measured at a temperature of the element formation layers (substrates) of 25° C. and V_(d) of 10 V.

In the negative BT test, first, V_(g)−I_(d) characteristics of the transistors were measured at a temperature of the element formation layers (substrates) of 25° C. and V_(d) of 10 V. Then, the temperature of the element formation layers (substrates) was set to 150° C. and V_(d) was set to 0.1 V. After that, V_(g) of −20 V was applied so that the intensity of an electric field applied to the gate insulating layers was −2 MV/cm, and the condition was kept for 1 hour. Next, V_(g) was set to 0 V. Then, V_(g)−I_(d) characteristics of the transistors were measured at a temperature of the element formation layers (substrates) of 25° C. and V_(d) of 10 V.

FIGS. 19A and 19B show the result of the positive BT test of Sample 1 and the result of the negative BT test of Sample 1, respectively. FIGS. 20A and 20B show the result of the positive BT test of Sample 2 and the result of the negative BT test of Sample 2, respectively.

As shown in FIGS. 19A and 19B, the amount of shift in the threshold voltage of Sample 1 due to the positive BT test and that due to the negative BT test were 1.80 V and −0.42 V, respectively. As shown in FIGS. 20A and 20B, the amount of shift in the threshold voltage of Sample 2 due to the positive BT test and that due to the negative BT test were 0.79 V and 0.76 V, respectively. It is therefore found that in both Sample 1 and Sample 2, the amount of shift in the threshold voltage of the transistor between before and after the BT tests is small and the reliability is high.

In addition, when an oxide semiconductor film that is formed by sputtering using a metal oxide target having a composition ratio of In:Sn:Zn=1:1:1 without heating an element formation layer intentionally is analyzed by X-ray diffraction (XRD), a halo pattern is observed. However, the oxide semiconductor film can be crystallized by being subjected to heat treatment. The temperature of the heat treatment at that time can be set as appropriate; when the heat treatment is performed at 650° C., for example, a clear diffraction peak can be observed in X-ray diffraction.

Here, the results of XRD measurement of an In—Sn—Zn—O film are shown below. The XRD measurement was conducted using an X-ray diffractometer D8 ADVANCE manufactured by Bruker AXS, and the measurement was performed by an out-of-plane method.

Sample A and Sample B were prepared and the XRD measurement was performed thereon. A method of fabricating Sample A and Sample B will be described below.

An In—Sn—Zn—O film with a thickness of 100 nm was formed over a quartz substrate that had been subjected to dehydrogenation treatment.

The In—Sn—Zn—O film was deposited with a sputtering apparatus with a power of 100 W (DC) in an oxygen atmosphere. As a target for the sputtering, an In—Sn—Zn—O target having an atomic ratio of In:Sn:Zn=1:1:1 was used. The heating temperature at the deposition was 200° C. A sample fabricated in the above step was Sample A.

Next, a sample fabricated by a method similar to that of Sample A was subjected to heat treatment at 650° C. Here, heat treatment in a nitrogen atmosphere was performed for 1 hour and then, heat treatment in an oxygen atmosphere was performed for 1 hour without lowering the temperature. A sample fabricated in the above steps was Sample B.

FIG. 21 shows XRD spectra of Sample A and Sample B. No peak derived from a crystal was observed in Sample A, whereas peaks derived from a crystal were observed when 2θ was around 35° and at 37° to 38° in Sample B. This means that the crystallinity of the oxide semiconductor layer is increased by at least one of the heat treatment during the deposition of the oxide semiconductor film containing In, Sn, and Zn as its main components and the heat treatment after the deposition.

By performing at least one of the heat treatment during the deposition of the oxide semiconductor film and the heat treatment after the deposition, the off-state current of the fabricated transistor per micrometer of channel width was 0.1 aA (1×10⁻¹⁹ A) or lower and 10 zA (1×10⁻²⁰ A) or lower when the temperature of the element formation layer (substrate) was 125° C. and 85° C., respectively, as shown in FIG. 22, for example. The proportional relation between the logarithm of the off-state current and the inverse of the temperature suggests that the off-state current of the above transistor per micrometer of channel width at room temperature (27° C.) is 0.1 zA (1×10⁻²² A) or lower. Hence, the off-state current of the above transistor per micrometer of channel width can be 1 aA (1×10⁻¹⁸ A) or lower, 100 zA (1×10⁻¹⁹ A) or lower, and 1 zA (1×10⁻²¹ A) or lower at 125° C., 85° C., and room temperature (27° C.), respectively.

Although hydrogen can be removed from an oxide semiconductor film containing In, Sn, and Zn as its main components by heat treatment, a film that does not contain impurities inherently is preferably formed because moisture is released from the oxide semiconductor film at a higher temperature than from an oxide semiconductor containing In, Ga, and Zn as its main components.

In addition, the relation between the temperature of the element formation layer (substrate) and electrical characteristics of a sample, on which heat treatment at 650° C. was performed after formation of the oxide semiconductor film, was evaluated.

The transistor used for the measurement has a channel length L of 3 μm, a channel width W of 10 μm, L_(ov) of 3 μm on one side (total L_(ov) of 6 μm), and dW of 0 μm. Note that V_(d) was 10 V. The measurement was performed under the following six conditions: the temperatures of the element formation layer (substrate) were −40° C., −25° C., 25° C., 75° C., 125° C., and 150° C. Note that L_(ov) represents the length in the channel length direction of a portion where a gate electrode overlaps with one of a pair of source and drain electrodes, and dW represents the width of a portion of the pair of electrodes in the channel width direction, which does not overlap with an oxide semiconductor film.

FIG. 23 shows the V_(g) dependence of I_(d) (solid line) and the field-effect mobility (dotted line). FIG. 24A shows the relation between the threshold voltage and the temperature of the element formation layer (substrate). FIG. 24B shows the relation between the field-effect mobility and the temperature of the element formation layer (substrate).

From FIG. 23 and FIG. 24A, it is found that the threshold voltage gets lower as the temperature of the element formation layer (substrate) increases. Note that the threshold voltage is decreased from 1.09 V to −0.23 V in the range from −40° C. to 150° C.

From FIG. 23 and FIG. 24B, it is found that the field-effect mobility gets lower as the temperature of the element formation layer (substrate) increases. Note that the field-effect mobility is decreased from 36 cm²/V·s to 32 cm²/V·s in the range from −40° C. to 150° C. Thus, it is found that variation in electrical characteristics is small in the above temperature range.

The above is the description of the transistors including the oxide semiconductor layer containing In, Sn, and Zn.

In the transistor including the oxide semiconductor layer containing In, Sn, and Zn as its main components, the field-effect mobility can be 30 cm²/V·s or higher, preferably 40 cm²/V·s or higher, more preferably 60 cm²/V·s or higher with the off-state current maintained at 1 aA/μm or lower, and can have on-state current high enough to meet the specifications demanded for LSI's. For example, in a transistor with a channel width of 40 nm and a channel length of 33 nm, an on-state current of 12 μA or higher can flow when the gate voltage is 2.7 V and the drain voltage is 1.0 V. Moreover, the transistor can have favorable electrical characteristics in the operating temperature range of transistors. Since the transistor including the oxide semiconductor layer has such characteristics, even when the transistor including the oxide semiconductor layer is included in a circuit constituted by transistors including semiconductor layers containing a semiconductor of Group 14 (e.g., silicon), a circuit having a novel function can be provided without decreasing the operation speed.

(Embodiment 4)

This embodiment will show an example of an arithmetic processing unit such as a CPU.

An example of the arithmetic processing unit in this embodiment is described with reference to FIG. 25.

The arithmetic processing unit in FIG. 25 includes a bus interface (also referred to as IF) 801, a control unit (also referred to as CTL) 802, a cache memory (also referred to as CACH) 803, an instruction decoder (also referred to as IDecoder) 805, and an arithmetic logic unit (also referred to as ALU) 806.

The bus interface 801 has a function of transmitting and receiving signals with an external unit and a function of exchanging signals with circuits in the arithmetic processing unit, and the like.

The control unit 802 has a function of controlling operations of the circuits in the arithmetic processing unit.

For example, the control unit 802 can include the arithmetic circuit in any of the above embodiments.

The cache memory 803 is controlled by the control unit 802 and has a function of temporary retaining data during the operation of the arithmetic processing unit. Note that the arithmetic processing unit may include a plurality of cache memory 803 as a primary cache and a secondary cache, for example.

The instruction decoder 805 has a function of translating an instruction signal which is read. The translated instruction signal is input to the control unit 802, and the control unit 802 outputs a control signal in accordance with the instruction signal to the arithmetic logic unit 806.

For example, the instruction decoder 805 can include the arithmetic circuit in any of the above embodiments.

The arithmetic logic unit 806 is controlled by the control unit 802 and has a function of performing logic operation processing in accordance with the input instruction signal.

For example, the arithmetic logic unit 806 can include the arithmetic circuits in any of the above embodiments.

Note that a register may be provided in the arithmetic processing unit. In that case, the register is controlled by the control unit 802. For example, a plurality of registers may be provided in the arithmetic processing unit, and some registers may be used for the arithmetic logic unit 806 and other registers may be used for the instruction decoder 805.

As described with reference to FIG. 25, the arithmetic processing unit exemplified in this embodiment includes the arithmetic circuit in any of the above embodiments in a unit such as the control unit, the instruction decoder, or the arithmetic logic unit, so that each unit can hold data in each unit and the processing speed can be increased.

Further, in the arithmetic processing unit exemplified in this embodiment, the arithmetic circuit in the above embodiment allows the data to be held for a long time while saving power. Accordingly, the power consumption of the arithmetic processing unit can be reduced. Further, the arithmetic processing unit including the arithmetic circuit in this embodiment can have a smaller area.

(Embodiment 5)

This embodiment will show examples of electronic appliances each provided with the arithmetic processing unit of any of the above embodiments.

Structural examples of the electronic appliances of this embodiment will be described with reference to FIGS. 26A to 26D.

An electronic appliance in FIG. 26A is an example of a mobile information terminal. The mobile information terminal in FIG. 26A includes a housing 1001 a and a display portion 1002 a provided in the housing 1001 a.

Note that a side surface 1003 a of the housing 1001 a may be provided with one or both of a connection terminal for connecting the mobile information terminal to an external device and a button for operating the mobile information terminal in FIG. 26A.

The housing 1001 a of the mobile information terminal in FIG. 26A includes a CPU, a storage circuit, an interface for transmitting and receiving signals between the external device and each of the CPU and the storage circuit, and an antenna for transmitting and receiving the signals to and from the external device.

The mobile information terminal in FIG. 26A serves as one or more of a telephone set, an e-book reader, a personal computer, and a game machine, for example.

An electronic appliance in FIG. 26B is an example of a folding mobile information terminal. The mobile information terminal in FIG. 26B includes a housing 1001 b, a display portion 1002 b provided in the housing 1001 b, a housing 1004, a display portion 1005 provided in the housing 1004, and a hinge 1006 for connecting the housing 1001 b and the housing 1004.

In the mobile information terminal in FIG. 26B, the housing 1001 b can be stacked on the housing 1004 by moving the housing 1001 b or the housing 1004 with the hinge 1006.

Note that a side surface 1003 b of the housing 1001 b or a side surface 1007 of the housing 1004 may be provided with one or both of a connection terminal for connecting the mobile information terminal to an external device and a button for operating the mobile information terminal in FIG. 26B.

The display portion 1002 b and the display portion 1005 may display different images or one image. Note that the display portion 1005 is not necessarily provided, and a keyboard which is an input device may be provided instead of the display portion 1005.

The housing 1001 b or the housing 1004 of the mobile information terminal in FIG. 26B includes a CPU, a storage circuit, and an interface for transmitting and receiving signals between the external device and each of the CPU and the storage circuit. Note that the mobile information terminal in FIG. 26B may include an antenna an antenna for transmitting and receiving the signals to and from the external device.

The mobile information terminal in FIG. 26B serves as one or more of a telephone set, an e-book reader, a personal computer, and a game machine, for example.

An electronic appliance in FIG. 26C is an example of a stationary information terminal. The stationary information terminal illustrated in FIG. 26C includes a housing 1001 c and a display portion 1002 c provided in the housing 1001 c.

Note that the display portion 1002 c can be provided on a countertop portion 1008 of the housing 1001 c.

The stationary information terminal in FIG. 26C includes a CPU, a storage circuit, and an interface for transmitting and receiving signals between the external device and each of the CPU and the storage circuit in the housing 1001 c. Note that the stationary information terminal in FIG. 26C may include an antenna for transmitting and receiving the signals to and from the external device.

Further, a side surface 1003 c of the housing 1001 c in the stationary information terminal in FIG. 26C may be provided with one or more portions selected from a ticket ejection portion that ejects a ticket or the like, a coin slot portion, and a bill slot portion.

The stationary information terminal in FIG. 26C serves, for examples, as an automated teller machine, an information communication terminal for ticketing or the like (also referred to as multi-media station), or a game machine.

FIG. 26D illustrates an example of a stationary information terminal. The stationary information terminal in FIG. 26D includes a housing 1001 d and a display portion 1002 d provided in the housing 1001 d. Note that a support for supporting the housing 1001 d may also be provided.

Note that a side surface 1003 d of the housing 1001 d may be provided with one or both of a connection terminal for connecting the stationary information terminal to an external device and a button for operating the stationary information terminal in FIG. 26D.

The stationary information terminal in FIG. 26D includes a CPU, a storage circuit, and an interface for transmitting and receiving signals between the external device and each of the CPU and the storage circuit in the housing 1001 d. Note that the stationary information terminal in FIG. 26D may include an antenna for transmitting and receiving the signals to and from the external device.

The stationary information terminal in FIG. 26D serves as a digital photoframe, a monitor, or a television set, for example.

The arithmetic processing unit in the above embodiment is used as the CPU in any of the electronic appliances in FIGS. 26A to 26D.

As described with reference to FIGS. 26A to 26D, the examples of the electronic appliances in this embodiment each include the arithmetic processing unit in the above embodiment as the CPU.

Further, in the electronic appliances exemplified in this embodiment, the arithmetic processing unit in the above embodiment allows the data to be held for a long time while saving power. Accordingly, the power consumption of the arithmetic processing unit can be reduced. Further, the arithmetic processing unit including the arithmetic circuit in this embodiment can have a smaller area.

This application is based on Japanese Patent Application serial no. 2011-112834 filed with Japan Patent Office on May 19, 2011, the entire contents of which are hereby incorporated by reference. 

What is claimed is:
 1. A semiconductor device comprising: a first line to which a first power supply potential is applied; a first transistor that includes an oxide semiconductor layer including a channel that includes an oxide semiconductor, wherein one of a source and a drain of the first transistor is electrically connected to the first line; a second transistor that includes an oxide semiconductor layer including a channel that includes an oxide semiconductor, wherein one of a source and a drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor; a circuit electrically connected to the other of the source and the drain of the second transistor; and a second line to which a second power supply potential is applied, the second line electrically connected to the circuit, wherein the first transistor is an n-channel transistor, and the second transistor is an n-channel transistor, wherein the circuit is configured to control whether the other of the source and the drain of the second transistor and the second line are brought into conduction or not, wherein the circuit comprises: a third transistor whose one of a source and a drain is electrically connected to the other of the source and the drain of the second transistor; and a fourth transistor whose one of a source and a drain is electrically connected to the other of the source and the drain of the third transistor, wherein the other of the source and the drain of the fourth transistor is electrically connected to the second line, wherein at least one of the first transistor and the second transistor comprises: a gate electrode over the oxide semiconductor layer; a source electrode over the oxide semiconductor layer; and a drain electrode over the oxide semiconductor layer; wherein the oxide semiconductor layer comprises a first n-type semiconductor region below the source electrode, a second n-type semiconductor region below the drain electrode, and a semiconductor region below the gate electrode, the semiconductor region being located between the first n-type semiconductor region and the second n-type semiconductor region.
 2. The semiconductor device according to claim 1, wherein at least one of the channel of the first transistor and the channel the second transistor comprises c-axis aligned crystals of the oxide semiconductor.
 3. The semiconductor device according to claim 1, wherein the first power supply potential is higher than the second power supply potential.
 4. The semiconductor device according to claim 1, wherein a first clock signal is input to a gate of the first transistor, and wherein a second clock signal which is a signal different from the first clock signal is input to a gate of the second transistor.
 5. The semiconductor device according to claim 1, further comprising: an element electrically connected to the other of the source and the drain of the first transistor and the one of the source and the drain of the second transistor.
 6. The semiconductor device according to claim 1, wherein the oxide semiconductor of the first transistor is an In-Ga-Zn-based oxide semiconductor, and wherein the oxide semiconductor of the second transistor is an In-Ga-Zn-based oxide semiconductor.
 7. A semiconductor device comprising: a first line to which a first power supply potential is applied; a first transistor that includes an oxide semiconductor layer including a channel that includes an oxide semiconductor, wherein one of a source and a drain of the first transistor is electrically connected to the first line; a second transistor that includes an oxide semiconductor layer including a channel that includes an oxide semiconductor, wherein one of a source and a drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor; a circuit electrically connected to the other of the source and the drain of the second transistor; and a second line to which a second power supply potential is applied, the second line electrically connected to the circuit, wherein the first transistor is an n-channel transistor, and the second transistor is an n-channel transistor, wherein the circuit is configured to control whether the other of the source and the drain of the second transistor and the second line are brought into conduction or not, wherein the circuit comprises: a third transistor whose one of a source and a drain is electrically connected to the other of the source and the drain of the second transistor; and a fourth transistor whose one of a source and a drain is electrically connected to the other of the source and the drain of the second transistor, wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor, wherein at least one of the first transistor and the second transistor comprises: a gate electrode over the oxide semiconductor layer; a source electrode over the oxide semiconductor layer; and a drain electrode over the oxide semiconductor layer; wherein the oxide semiconductor layer comprises a first n-type semiconductor region below the source electrode, a second n-type semiconductor region below the drain electrode, and a semiconductor region below the gate electrode, the semiconductor region being located between the first n-type semiconductor region and the second n-type semiconductor region.
 8. The semiconductor device according to claim 7, further comprising: a fifth transistor whose one of a source and a drain is electrically connected to the other of the source and the drain of the third transistor; a sixth transistor whose one of a source and a drain is electrically connected to the other of the source and the drain of the second transistor; a seventh transistor whose one of a source and a drain is electrically connected to the other of the source and the drain of the sixth transistor; an eighth transistor whose one of a source and a drain is electrically connected to the other of the source and the drain of the seventh transistor.
 9. The semiconductor device according to claim 7, further comprising: a fifth transistor whose one of a source and a drain is electrically connected to the other of the source and the drain of the third transistor; a sixth transistor whose one of a source and a drain is electrically connected to the other of the source and the drain of the third transistor; a seventh transistor whose one of a source and a drain is electrically connected to the other of the source and the drain of the fifth transistor and the other of the source and the drain of the sixth transistor; an eighth transistor whose one of a source and a drain is electrically connected to the other of the source and the drain of the second transistor; a ninth transistor whose one of a source and a drain is electrically connected to the other of the source and the drain of the eighth transistor; a tenth transistor whose one of a source and a drain is electrically connected to the other of the source and the drain of the second transistor; an eleventh transistor whose one of a source and a drain is electrically connected to the other of the source and the drain of the tenth transistor; and a twelfth transistor whose one of a source and a drain is electrically connected to the other of the source and the drain of the ninth transistor and the other of the source and the drain of the eleventh transistor.
 10. The semiconductor device according to claim 7, wherein at least one of the channel of the first transistor and the channel the second transistor comprises c-axis aligned crystals of the oxide semiconductor.
 11. The semiconductor device according to claim 7, wherein the first power supply potential is higher than the second power supply potential.
 12. The semiconductor device according to claim 7, wherein a first clock signal is input to a gate of the first transistor, and wherein a second clock signal which is a signal different from the first clock signal is input to a gate of the second transistor.
 13. The semiconductor device according to claim 7, further comprising: an element electrically connected to the other of the source and the drain of the first transistor and the one of the source and the drain of the second transistor.
 14. The semiconductor device according to claim 7, wherein the oxide semiconductor of the first transistor is an In—Ga—Zn-based oxide semiconductor, and wherein the oxide semiconductor of the second transistor is an In—Ga—Zn-based oxide semiconductor.
 15. A semiconductor device comprising: a first line to which a first power supply potential is applied; a first transistor that includes an oxide semiconductor layer including a channel that includes an oxide semiconductor, wherein one of a source and a drain of the first transistor is electrically connected to the first line; a second transistor that includes an oxide semiconductor layer including a channel that includes an oxide semiconductor, wherein one of a source and a drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor; a circuit electrically connected to the other of the source and the drain of the second transistor; and a second line to which a second power supply potential is applied, the second line electrically connected to the circuit, wherein the first transistor is an n-channel transistor, and the second transistor is an n-channel transistor, wherein the circuit is configured to control whether the other of the source and the drain of the second transistor and the second line are brought into conduction or not, wherein the circuit comprises: a third transistor whose one of a source and a drain is electrically connected to the other of the source and the drain of the second transistor; a fourth transistor whose one of a source and a drain is electrically connected to the other of the source and the drain of the third transistor; a fifth transistor whose one of a source and a drain is electrically connected to the other of the source and the drain of the second transistor; and a sixth transistor whose one of a source and a drain is electrically connected to the other of the source and the drain of the fifth transistor, wherein the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the sixth transistor, wherein at least one of the first transistor and the second transistor comprises: a gate electrode over the oxide semiconductor layer; a source electrode over the oxide semiconductor layer; and a drain electrode over the oxide semiconductor layer; wherein the oxide semiconductor layer comprises a first n-type semiconductor region below the source electrode, a second n-type semiconductor region below the drain electrode, and a semiconductor region below the gate electrode, the semiconductor region being located between the first n-type semiconductor region and the second n-type semiconductor region.
 16. The semiconductor device according to claim 15, wherein at least one of the channel of the first transistor and the channel the second transistor comprises c-axis aligned crystals of the oxide semiconductor.
 17. The semiconductor device according to claim 15, wherein the first power supply potential is higher than the second power supply potential.
 18. The semiconductor device according to claim 15, wherein a first clock signal is input to a gate of the first transistor, and wherein a second clock signal which is a signal different from the first clock signal is input to a gate of the second transistor.
 19. The semiconductor device according to claim 15, further comprising: an element electrically connected to the other of the source and the drain of the first transistor and the one of the source and the drain of the second transistor.
 20. The semiconductor device according to claim 15, wherein the oxide semiconductor of the first transistor is an In—Ga—Zn-based oxide semiconductor, and wherein the oxide semiconductor of the second transistor is an In—Ga—Zn-based oxide semiconductor. 